CACHE MEMORY AND CONTROL METHOD THEREOF

WIPO Patent Application WO/2011/049051

A1

Provided are a cache memory and a control method thereof, by which electric power consumption can be reduced without reducing a cache hit ratio. A CAM sub-tag address extraction unit (22a) extracts a CAM sub-tag address from a tag address. A SRAM sub-tag address extraction unit (22b) extracts a SRAM sub-tag address from the tag address. A CAM (51) retrieves data by comparing CAM sub-tag addresses. A comparison retrieval unit (71) retrieves data by comparing the extracted SRAM sub-tag address and the SRAM sub-tag address stored in the SRAM, with respect to recently read out first generation data among the data of the retrieved tag address. An output unit (72) outputs, as a response to a request, the first generation data which is retrieved by the comparison retrieval unit (71) and stored in association with the SRAM sub-tag address. The method can be applied to a cache memory.

OKABE SHO (JP)
ABE KOKI (JP)

PCT/JP2010/068298

April 28, 2011

October 19, 2010

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UNIV ELECTRO COMMUNICATIONS (JP)
OKABE SHO (JP)
ABE KOKI (JP)

G06F12/08; G06F12/12; G11C15/04

JP2003519835A	2003-06-24
JPS62293596A	1987-12-21
JPH06131265A	1994-05-13
JPH0535599A	1993-02-12
JP3850669B2	2006-11-29
JPH08263370A	1996-10-11

See also references of EP 2492818A4
ZHANG, C.: "A Low Power Highly Associative Cache for Embedded Systems", PROC. IEEE ICCD, 2006, pages 31 - 36, XP031159204
ITOH, K.; SASAKI, K.; NAKAGOME, Y.: "Trends in low-power RAM circuit technologies", PROCEEDINGS OF THE IEEE, vol. 83, no. 4, 1995, pages 524 - 543

INAMOTO Yoshio et al. (JP)
Yoshio Inemoto (JP)

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