Title:
CACHE MEMORY WITH VARIABLE WRITE PULSE WIDTH
Document Type and Number:
WIPO Patent Application WO/2015/133643
Kind Code:
A1
Abstract:
[Problem] To enable a reduction in the average latency in access time and enable lower power consumption. [Solution] A cache memory equipped with: a data cache unit storing data in units of cache lines; a tag unit storing address information for the data stored in the data cache unit; a cache controller that determines whether an address to which access has been requested from a processor matches address information stored in the tag unit, and controls access to the data cache and the tag unit on the basis of the result of that determination; and a write period control unit that controls the period required for writing data to the cache unit, on the basis of the error frequency when reading data stored in the data cache unit or the degree of the decrease in the processing performance of the processor due to a delay in reading data stored in the cache unit.
Inventors:
NOGUCHI HIROKI (JP)
TANAMOTO TETSUFUMI (JP)
IKEGAMI KAZUTAKA (JP)
FUJITA SHINOBU (JP)
TANAMOTO TETSUFUMI (JP)
IKEGAMI KAZUTAKA (JP)
FUJITA SHINOBU (JP)
Application Number:
PCT/JP2015/056824
Publication Date:
September 11, 2015
Filing Date:
March 09, 2015
Export Citation:
Assignee:
TOSHIBA KK (JP)
International Classes:
G06F12/16; G06F12/08
Foreign References:
| JP2012022726A | 2012-02-02 | |||
| JP2014110073A | 2014-06-12 | |||
| JP2015049918A | 2015-03-16 |
Attorney, Agent or Firm:
KATSUNUMA Hirohito et al. (JP)
Katsunuma Hirohito (JP)
Katsunuma Hirohito (JP)
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