Title:
A CAM MEMORY
Document Type and Number:
WIPO Patent Application WO/2018/015839
Kind Code:
A3
Abstract:
A CAM memory (Content Addressable Memory) is described, comprising a plurality of memory cells (2), organized in rows and columns, adapted to store a plurality of data words, a plurality of bit lines (BL, BLN) for receiving the bits of a word to be stored, a plurality of write lines (WL, WLN) to enable writing of a sequence of memory cells, so as to store the bits present on the bit lines (BL, BLN), a plurality of search lines (SL, SLN) arranged in the column direction to transmit a word to be searched in the memory cells, a matching circuit to compare bits of the word to be searched with bits of the words stored in the memory cells. At least two of the write lines (WL0, WL1) are intertwined, so that on a same row of the CAM memory (10) are stored alternately bits of at least two different words. In this way, the length of the search lines and/ or of the bit lines can be reduced.
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Inventors:
STABILE ALBERTO (IT)
ANNOVI ALBERTO (IT)
FRONTINI LUCA (IT)
LIBERALI VALENTINO (IT)
ANNOVI ALBERTO (IT)
FRONTINI LUCA (IT)
LIBERALI VALENTINO (IT)
Application Number:
PCT/IB2017/054171
Publication Date:
April 12, 2018
Filing Date:
July 11, 2017
Export Citation:
Assignee:
ISTITUTO NAZ FISICA NUCLEARE (IT)
International Classes:
G11C15/00; G11C8/14; G11C15/04
Foreign References:
| US7286379B1 | 2007-10-23 | |||
| US20090175064A1 | 2009-07-09 | |||
| US20130170273A1 | 2013-07-04 | |||
| US20040100830A1 | 2004-05-27 | |||
| US8493763B1 | 2013-07-23 |
Other References:
ANNOVI ALBERTO ET AL: "A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications", 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), IEEE, 6 December 2015 (2015-12-06), pages 392 - 395, XP032884812, DOI: 10.1109/ICECS.2015.7440331
PAGIAMTZIS K ET AL: "A Low-Power Content-Addressable Memory (CAM) Using Pipelined Hierarchical Search Scheme", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 39, no. 9, 30 August 2004 (2004-08-30), pages 1512 - 1519, XP011117971, ISSN: 0018-9200, DOI: 10.1109/JSSC.2004.831433
PAGIAMTZIS K ET AL: "A Low-Power Content-Addressable Memory (CAM) Using Pipelined Hierarchical Search Scheme", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 39, no. 9, 30 August 2004 (2004-08-30), pages 1512 - 1519, XP011117971, ISSN: 0018-9200, DOI: 10.1109/JSSC.2004.831433
Attorney, Agent or Firm:
LISA, Elisabetta et al. (IT)
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