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Title:
CAPACITANCE-TO-VOLTAGE CONVERSION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2015/115264
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a capacitance-to-voltage conversion circuit that makes it possible to maintain a capacitance-to-voltage conversion processing time, reduce power consumption, and reduce noise. In synchronization with two consecutive sampling periods of a first sample-and-hold circuit (12), a second sample-and-hold circuit (14) simultaneously samples and holds, in a second capacitive element (Cout3), the positive-phase output voltage (VOp) and negative-phase output voltage (VOn) of a differential amplifier (15), which are sampled and held by the first sample-and-hold circuit (12). Next, in a separate sampling period, the second sample-and-hold circuit (14) connects the second capacitive element (Cout3), which has accumulated charge in advance, to a positive-phase capacitive element (Cout1) and negative-phase capacitive element (Cout2) of the first sample-and-hold circuit (12) immediately before the positive-phase and negative-phase capacitive elements (Cout1, Cout2) are held at a desired level. At this time, the load capacitance connected to the output of the differential amplifier (15) is increased and a band is narrowed.

Inventors:
OKAMI, Tsuyoshi (10-1 Nakazawa-cho, Naka-ku, Hamamatsu-sh, Shizuoka 50, 〒4308650, JP)
Application Number:
JP2015/051472
Publication Date:
August 06, 2015
Filing Date:
January 21, 2015
Export Citation:
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Assignee:
MURATA MANUFACTURING CO., LTD. (10-1, Higashikotari 1-chome Nagaokakyo-sh, Kyoto 55, 〒6178555, JP)
International Classes:
G01R27/26; G01P15/125
Foreign References:
JP2004279261A2004-10-07
JP2012037439A2012-02-23
Attorney, Agent or Firm:
SAMEJIMA, Mutsumi et al. (AOYAMA & PARTNERS, Umeda Hankyu Bldg. Office Tower 8-1, Kakuda-cho, Kita-ku, Osaka-sh, Osaka 17, 〒5300017, JP)
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