TECHNICAL FIELD

[0001] The present application generally relates to capacitive micromachined ultrasonic transducer arrays, and more specifically to a fabrication methodology for those transducer arrays using pre-fabricated and interconnected substrates such as printed circuit boards (PCBs).

BACKGROUND

[0002] Ultrasound systems have traditionally used piezoelectric materials for their transducers since the 1930s. Materials such as piezoelectric crystals (e.g., quartz), ceramics (e.g., lead zirconate titanate [PZT]) and polymers (e.g., polyvinylidene fluoride [PVDF]) are known transducer materials [1 ]. Despite the fact that piezoelectric transducers technology is mature, it suffers from many drawbacks, such as the technical challenges in fabricating large two-dimensional arrays due to interconnection and integration challenges [1] at the die-level.

[0003] Acoustic impedance (the speed of sound in a material multiplied by its density, measured in Rayls) is a measure of the opposition that a system presents to the acoustic pressure applied to the system. It is an important quantity in piezoelectricbased ultrasound systems, since it determines how much acoustic power is effectively transferred to a target material being imaged. An “acoustic matching layer” is a mandatory structure in piezoelectric-based systems to reduce the impedance mismatch between the impedance of the piezoelectric crystals and the lower or higher impedance of the target materials (e.g., tissues or metals). These matching layers are typically made of high-density rubber combined with liquid gel, and are located between the crystals and the target material.

[0004] Capacitive micromachined ultrasonic transducers (CMUTs) are an alternative technology to the current piezoelectric-based transducers [1 ], A CMUT is essentially a parallel-plate capacitor with an electrode at its bottom fixed to a substrate, and with a membrane suspended over a cavity and sealed along its edges. A metallic electrode is patterned on top of the suspended membrane. Ultrasound waves are generated by a CMUT when an AC signal superimposed on a DC voltage is applied across the electrodes. Ultrasound waves can be detected by measuring the variation in capacitance of the device while a DC voltage is applied in the presence of incoming ultrasound. Most CMUTs are made of a silicon-based material on a silicon substrate. However, silicon has a higher acoustic impedance than soft tissue, and a lower acoustic impedance than metals or composites, so even with CMUTs there is still an acoustic mismatch.

[0005] United States patent nos. 10,509,013, 10,564,132, and 10,598,632, the entireties of all of which are hereby incorporated by reference herein, describe the microfabrication of ultrasonic transducers using polymer membranes. These polymer- based CMUTs (polyCMUTs) can in at least some cases operate using lower operating voltages than piezoelectric transducers or silicon-based CMUTs.

[0006] United States patent nos. 10,509,013, 10,564,132, and 10,598,632 collectively describe two ways of microfabricating CMUTs: surface micromachining and wafer-bonding. In surface micromachining, the cavity underneath the membrane is created by depositing or growing a sacrificial layer on the carrier substrate. After membrane deposition, the sacrificial layer is removed with an etchant that is specifically chosen to dissolve the sacrificial material via etch channels without damaging the membrane material. In wafer-bonding, the membrane and the cavity are defined on separate wafers that are bonded together under vacuum conditions. Given that etching channels are not required, the fabrication process is simplified, and a higher fill factor can be achieved.

[0007] Silicon nitride and polysilicon are the most popular materials for fabricating CMUT membranes, while chromium and aluminum are typically used to pattern electrodes on top of these membranes. These materials are chosen mainly for their mechanical properties, such that the membranes can be as thin as possible, in order to minimize the effective gap between the bottom and top (or “hot”) electrodes. By decreasing the effective gap between electrodes, the electric field can be increased, and the impedance matching to the electronics that drive the CMLIT can be improved. Once the desired operational frequency and the maximum biasing voltage have been identified, the CMLIT membranes are preferably designed as thick as possible, given that their bandwidths linearly increase with thickness.

[0008] Through Silicon Vias (TSVs) are vertical electrical interconnects that pass through a silicon wafer or chip, connecting different layers of circuitry. TSVs are used to enable better performance, smaller form factors, and higher integration in semiconductor devices. They offer several advantages, including reduced signal propagation delays, increased bandwidth, and the ability to connect multiple chip layers in a compact manner. The main limitation with TSVs is that they only permit communication between opposing sides of the substrate (front and rear) through a vertical conductive channel.

[0009] Printed Circuit Boards (PCBs) can facilitate routing in different layers through the use of vias and multi-layer construction. Through-hole vias go through the entire thickness of the PCB, connecting all layers. They are commonly used for components and traces that require strong connections. Blind and buried vias connect only specific layers of the PCB. Blind vias connect an outer layer to one or more inner layers, while buried vias connect two or more inner layers. Both types of vias allow for more complex routing without affecting the outer layers. Modem PCBs often consist of multiple layers of copper traces separated by insulating material in the form of the PCB’s substrate. The inner layers are sandwiched between the outer layers. Each layer can be used for routing, power planes, or ground planes.

[00010] PCBs can be fabricated using materials such as FR-4 (fiberglass-reinforced epoxy), high-Tg materials for elevated temperatures, flexible materials like polyimide and polyester, rigid-flex materials combining rigidity and flexibility, metal core materials for improved heat dissipation, ceramic materials for high-temperature stability, RF/microwave materials for high-frequency applications, and specialized materials like Teflon™ (PTFE) for specific performance requirements. The choice depends on factors such as application, thermal management, operating frequency, and desired electrical and mechanical properties.

[00011] Low-temperature co-fired ceramic, or LTCC, is a ceramic electronics technology used for ceramic PCB or PCBA (i.e. , a PCB assembly with all components on the PCB) fabrication. LTCC, developed from the HTCC (high-temperature co-fired ceramic) technology in 1982, is a multilayer low-temperature ceramic PCB manufacturing technology. HTCC is a ceramic based on alumina (AI2O3) and aluminum nitride (AIN). LTCC is a ceramic in which glass is mixed into alumina, and is also generally referred to as “glass ceramics”. HTCC substrates are cured at a temperature of 1500 °C or higher. In order to cure at a high temperature, tungsten (W) and molybdenum (Mo), which have high melting points, are used for the circuit electrodes. For LTCC substrates, the curing temperature can be decreased down to 900 °C by mixing glass into the alumina ceramic. Thus, it is possible to use silver or copper, which have low conductivity, for wiring.

[00012] PCBs fabricated in FR-4 utilize a composite material of fiberglass and epoxy, offering moderate electrical insulation and mechanical strength, suitable for standard electronics. FR-4 is versatile and cost-effective for general-purpose electronics and can be manufactured by a great number of fabrication facilities around the world. In contrast, PCBs made with LTCC involve layering ceramic tapes with embedded conductors, resulting in superior electrical properties, high thermal stability, and suitability for high-frequency and high-temperature applications, making them ideal for RF modules, microwave devices, and sensors in demanding environments.

SUMMARY

[00013] According to an aspect of the disclosure, there is provided a method for manufacturing a capacitive micromachined ultrasonic transducer, the method comprising: removing a layer from a top side of a substrate, wherein at least a pair of electrical interconnects extend at least partially through the substrate and are exposed on the top side; after the removing, depositing a first electrically conductive material on the top side, wherein the first electrically conductive material covers the pair of electrical interconnects; patterning the first conductive material to form a bottom electrode and a contact area for a top electrode, wherein the bottom electrode is electrically connected to one of the pair of electrical interconnects and the contact area for the top electrode is electrically connected to the other of the pair of electrical interconnects; after the patterning, depositing a sacrificial material on the bottom electrode; patterning the sacrificial material to form a sacrificial membrane area connected to at least one sacrificial etch channel; after the sacrificial material is patterned, depositing a first polymer or silicon layer on the substrate, the bottom electrode, the contact area, and the sacrificial material; patterning the first polymer or silicon layer to form at least one via to the at least one sacrificial etch channel; depositing a second electrically conductive material on the first polymer or silicon layer and on the contact area for the top electrode; patterning the second electrically conductive material to avoid an electrical connection with the bottom electrode; and etching away the sacrificial membrane area using the at least one via.

[00014] The first polymer layer may be deposited on the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material after the sacrificial material is patterned, and the method may further comprise: depositing a second polymer layer on top of the second electrically conductive material and the sacrificial membrane area; and patterning the second polymer layer to avoid plugging the at least one via. Alternatively, the silicon layer may be deposited on the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material after the sacrificial material is patterned. [00015] The substrate may comprise a printed circuit board. The printed circuit board may be flexible.

[00016] The substrate may comprise a ceramic.

[00017] Removing the layer may be performed mechanically. For example, removing the layer may comprise polishing or grinding the top side of the substrate.

[00018] Removing the layer may be done chemically. For example, removing the layer may comprise etching the top side of the substrate.

[00019] Pads of conductive material may be respectively electrically coupled to the pair of electrical interconnects on the top side prior to removing the layer, and removing the layer may comprise removing the pads and part of the substrate.

[00020] After the removing, the top side may have a surface roughness of no more than 50 nanometers.

[00021] The first conductive material may comprise a layer of gold between two layers of chromium.

[00022] The first conductive material may have a thickness of approximately 100 nm.

[00023] The sacrificial material may be approximately 200 nm thick.

[00024] Depositing the sacrificial material may comprise depositing a layer of lift-off resist and then depositing a layer of positive photoresist.

[00025] Patterning the sacrificial material may be performed by wet etching using an aqueous solution comprising tetramethylammonium hydroxide.

[00026] The first polymer layer may be approximately 700 nm thick.

[00027] Depositing the second electrically conductive material may comprise depositing a layer of titanium and then depositing a layer of gold. [00028] The method may further comprise encapsulating the transducer with an encapsulation material.

[00029] A bottom side of the substrate may comprise pads of conductive material respectively electrically coupled to the pair of electrical interconnects, and the method may further comprise covering the pads on the bottom side prior to encapsulating the transducer to prevent the pads from being covered by the encapsulation material.

[00030] The method may further comprise, after the layer of the top side is removed and before depositing the first electrically conductive material: depositing a planarization layer on the top side; and patterning the planarization layer such that the electrical interconnects remain exposed on the top side.

[00031] The planarization layer may be approximately 1 pm thick.

[00032] The planarization layer may comprises Sll-8 photoresist.

[00033] The planarization layer may have a roughness of no more than 50 nanometers.

[00034] The method may further comprise, prior to removing the layer from the top side of the substrate: depositing a substrate conductive material on a surface of the substrate; patterning the substrate conductive material to form a substrate conductive area for the bottom electrode and a substrate conductive area for the top electrode, wherein the substrate conductive area for the bottom electrode is electrically connected to one of the pair of electrical interconnects and the other of the substrate conductive areas is electrically connected to the other of the pair of electrical interconnects; and depositing a planarization layer on the substrate and the substrate conductive areas; wherein the substrate conductive area and the contract area for the bottom electrode and electrically connected to the same electrical interconnect, and the substrate conductive area and the contract area for the top electrode and electrically connected to the same electrical interconnect, and wherein the layer that is removed from the top side of the substrate comprises the planarization layer above the substrate conductive material. [00035] The planarization layer may comprise an epoxy resin.

[00036] The planarization layer may have a thickness equal to or greater than a thickness of the substrate conductive material.

[00037] The method may further comprising, after depositing the planarization layer and before removing the layer from the top side of the substrate, de-gassing the planarization layer.

[00038] The planarization layer may comprise a solder mask layer of a printed circuit board.

[00039] The layer that is removed from the top side of the substrate may comprise an upper substrate layer adhered to the substrate. Between the substrate and the upper substrate layer may be a substrate conductive area for the bottom electrode and a substrate conductive area for the top electrode, wherein the substrate conductive area for the bottom electrode is electrically connected to one of the pair of electrical interconnects and the other of the substrate conductive areas is electrically connected to the other of the pair of electrical interconnects. The substrate conductive area and the contract area for the bottom electrode may be electrically connected to the same electrical interconnect, and the substrate conductive area and the contract area for the top electrode may be electrically connected to the same electrical interconnect.

[00040] The electrical interconnects may extend non-linearly through the substrate.

[00041] The capacitive micromachined ultrasonic transducer may be one of an array of capacitive micromachined ultrasonic transducers manufactured concurrently by the method.

[00042] According to another aspect of the disclosure, there is provided a capacitive micromachined ultrasonic transducer assembly comprising: a printed circuit board (PCB) comprising at least a pair of electrical interconnects that extend at least partially through the PCB and that are exposed on a top side of the PCB; a capacitive micromachined ultrasonic transducer cell on the PCB, wherein the capacitive micromachined ultrasonic transducer cell comprises: a bottom electrode electrically connected on the top side to one of the pair of electrical interconnects; a top electrode electrically connected on the top side to the other of the pair of electrical interconnects; a polymer or silicon layer between the top and bottom electrodes; and a sealed cavity between the polymer or silicon layer and the bottom electrode.

[00043] The PCB may be flexible. Alternatively, the PCB may comprise a ceramic.

[00044] The bottom electrode may be directly on the PCB. Alternatively, the bottom electrode may be on a planarization layer.

[00045] The bottom electrode may be on a planarization layer and the planarization layer may comprise solder mask.

[00046] The bottom electrode may be co-planar with a portion of a layer of the PCB.

[00047] The bottom electrode may be co-planar with a portion of a planarization layer.

[00048] The bottom electrode may be co-planar with a bottom portion of the polymer or silicon layer.

[00049] The capacitive micromachined ultrasonic transducer cell may be one of an array of capacitive micromachined ultrasonic transducer cells. The array may comprise capacitive micromachined ultrasonic transducer elements corresponding to different groups selected from the plurality of capacitive micromachined ultrasonic transducer cells, and the capacitive micromachined ultrasonic transducer elements may be respectively electrically connected to the electrical interconnects.

[00050] The polymer layer may be between the top and bottom electrodes. Alternatively, the silicon layer may be between the top and bottom electrodes.

[00051] The electrical interconnects may extend non-linearly through the substrate. [00052] According to another aspect of the disclosure, there is provided an apparatus comprising: a printed circuit board with exposed interconnections; and a polymer-based capacitive micro machined ultrasonic structure having connections positioned on the exposed interconnections of the printed circuit board.

[00053] The printed circuit board may have a roughness of less than one micrometer.

[00054] The polymer-based capacitive micro machined ultrasonic structure may be a transducer.

[00055] The polymer-based capacitive micro machined ultrasonic structure may be a sensor.

[00056] The polymer-based capacitive micro machined ultrasonic structure may be a receiver.

[00057] The printed circuit board may comprise a layer of polishable material.

[00058] The layer of polishable material may be polished to achieve a roughness of less than one micrometer.

[00059] According to another aspect of the disclosure, there is provided a method comprising: obtaining a printed circuit board having a bottom electrode thereon, wherein the bottom electrode is positioned such that the bottom electrode is electrically coupled to a first via of the printed circuit board; depositing a sacrificial layer on top of the bottom electrode; depositing a first polymer layer on top of the sacrificial layer; depositing a top electrode on top of the first polymer layer, wherein the top electrode is deposited such that the top electrode is electrically coupled to a second via of the printed circuit board; depositing a second polymer layer on top of the top electrode; removing the sacrificial layer to result in a cavity; and encapsulating the bottom electrode, first polymer layer, top electrode, second polymer material, and cavity within an encapsulation material on the printed circuit board. The choice of material for the printed circuit board may be selected based on factors such as the intended application, budget, performance requirements, and manufacturing processes. Example materials comprise FR-4 (Flame Retardant 4), high-Tg (glass transition temperature) materials, flexible materials (e.g., polyimide and polyester), Rigid-Flex materials from Rigiflex Technology Inc., metal core materials (MCPCB), ceramic materials, and RF/microwave materials with low dielectric constants.

[00060] Obtaining the printed circuit board having the bottom electrode thereon may comprise depositing the bottom electrode on to the printed circuit board.

[00061] The method may further comprise polishing the printed circuit board prior to depositing the bottom electrode.

[00062] The printed circuit board may be polished to a roughness of less than one micrometer.

[00063] The method may further comprise depositing a planarization layer between the printed circuit board and the bottom electrode.

[00064] The method may further comprise depositing a planarization layer on the bottom electrode.

[00065] The method may further comprise polishing the planarization layer to obtain a polished surface of the bottom electrode prior to depositing the sacrificial layer.

[00066] Obtaining the printed circuit board having the bottom electrode thereon may comprise patterning the bottom electrode in an inner layer of the printed circuit board, and the method may further comprise grinding and polishing the printed circuit board to obtain a polished surface of the bottom electrode prior to depositing the sacrificial layer.

[00067] According to another aspect of the disclosure, there is provided an apparatus manufactured according to the above methods.

[00068] According to another aspect of the disclosure, there is provided an apparatus comprising: a printed circuit board comprising a polished surface and a pair of vias extending through the polished surface; and a polymer-based capacitive micro machined ultrasonic structure located on the polished surface and comprising a top electrode and a bottom electrode, wherein the top electrode is electrically coupled to one of the vias and the bottom electrode is electrically coupled to another of the vias. [00069] According to another aspect of the disclosure, there is provided an apparatus comprising: a printed circuit board fabricated using either low-temperature co-fired ceramic (LTCC) or high-temperature co-fired ceramic (HTCC) technology comprising a polished surface and a pair of vias extending through the polished surface; and a silicon-based capacitive micro machined ultrasonic structure located on the polished surface and comprising a top electrode and a bottom electrode, wherein the top electrode is electrically coupled to one of the vias and the bottom electrode is electrically coupled to another of the vias. The LTCC and HTCC technology allows silicon-based CMUTs to be manufactured since the process temperatures (above 900 °C) are compatible with standard deposition methods for silicon, polysilicon, silicon dioxide, and silicon nitride layers.

BRIEF DESCRIPTION OF THE DRAWINGS

[00070] Further features and advantages of the present disclosure will become apparent from the following detailed description, taken in combination with the appended drawings, in which:

[00071] Figure 1 A and Figure 1 B show the top and cross-sectional views respectively of a substrate with prefabricated conductive vias according to a first embodiment.

[00072] Figure 2A and Figure 2B show the top and cross-sectional views respectively of the substrate shown in Figure 1A and Figure 1 B after mechanically polishing the substrate, removing the annular rings and leaving a planarized surface.

[00073] Figure 3A and Figure 3B show the top and cross-sectional views respectively of the substrate shown in Figure 2A and Figure 2B after a first conductive layer was deposited and patterned, forming the bottom electrode of a polyCMUT cell.

[00074] Figure 4A and Figure 4B show the top and cross-sectional views respectively of the substrate shown in Figure 3A and Figure 3B after a sacrificial layer was deposited and patterned. This sacrificial layer will become the cavity of a polyCMUT cell.

[00075] Figure 5A and Figure 5B show the top and cross-sectional views respectively of the substrate shown in Figure 4A and Figure 4B after a first polymer layer was deposited and patterned.

[00076] Figure 6A and Figure 6B show the top and cross-sectional views respectively of the substrate shown in Figure 5A and Figure 5B after a second conductive layer is deposited and patterned.

[00077] Figure 7A and Figure 7B show the top and cross-sectional views respectively of the substrate shown in Figure 6A and Figure 6B after a second polymer layer was deposited and patterned, with the via holes on the first polymer layer remaining open so that the sacrificial layer can be etched. [00078] Figure 8A and Figure 8B show the top and cross-sectional views respectively of the substrate shown in Figure 7A and Figure 7B after the sacrificial layer has been etched in a solvent. The remaining structure is a CMLIT with a cavity filled with air.

[00079] Figure 9A and Figure 9B show the top and cross-sectional views respectively of the substrate shown in Figure 8A and Figure 8B after the assembly has been sealed by an encapsulation material deposited in a low-pressure chamber.

[00080] Figure 10A and Figure 10B show the top and cross-sectional views respectively of a substrate with prefabricated conductive vias according to a second embodiment.

[00081] Figure 11A and Figure 11 B show the top and cross-sectional views respectively of a substrate shown in Figure 10A and Figure 10B after mechanically polishing the substrate, removing the annular rings, and leaving a planarized surface.

[00082] Figure 12A and Figure 12B show the top and cross-sectional views respectively of the substrate shown in Figure 11 A and Figure 11 B after a planarization layer was deposited and patterned. The areas leading to the vias on the substrate remain open for subsequent processes.

[00083] Figure 13A and Figure 13B show the top and cross-sectional views respectively of the substrate shown in Figure 12A and Figure 12B after a first conductive layer was deposited and patterned, forming the bottom electrode of a polyCMUT cell.

[00084] Figure 14A and Figure 14B show the top and cross-sectional views respectively of the substrate shown in Figure 13A and Figure 13B after a sacrificial layer was deposited and patterned. This sacrificial layer will become the cavity of a polyCMUT cell. [00085] Figure 15A and Figure 15B show the top and cross-sectional views respectively of the substrate shown in Figure 14A and Figure 14B after a first polymer layer was deposited and patterned.

[00086] Figure 16A and Figure 16B show the top and cross-sectional views respectively of the substrate shown in Figure 15A and Figure 15B after a second conductive layer is deposited and patterned. An electrical connection is present between one of the via holes in the substrate and this second conductive layer.

[00087] Figure 17A and Figure 17B show the top and cross-sectional views respectively of the substrate shown in Figure 16A and Figure 16B after a second polymer layer was deposited and patterned; the via holes on the first polymer layer remain open so that the sacrificial layer can be etched.

[00088] Figure 18A and Figure 18B show the top and cross-sectional views respectively of the substrate shown in Figure 17A and Figure 17B after the sacrificial layer has been etched in a solvent. The remaining structure is a CMLIT with a cavity filled with air.

[00089] Figure 19A and Figure 19B show the top and cross-sectional views respectively of the substrate shown in Figure 18A and Figure 18B after the assembly has been sealed by an encapsulation material deposited in a low-pressure chamber.

[00090] Figure 20A and Figure 20B show the top and cross-sectional views respectively of a substrate with prefabricated conductive vias and a patterned conductive region in the center according to a third embodiment.

[00091] Figure 21 A and Figure 21 B show the top and cross-sectional views respectively of the substrate shown in Figure 20A and Figure 20B after a planarization layer was deposited and patterned.

[00092] Figure 22A and Figure 22B show the top and cross-sectional views respectively of a substrate shown in Figure 21 A and Figure 21 B after mechanically polishing the substrate, thereby removing a portion of the planarization layer. [00093] Figure 23A and Figure 23B show the top and cross-sectional views respectively of the substrate shown in Figure 22A and Figure 22B after a sacrificial layer was deposited and patterned.

[00094] Figure 24A and Figure 24B show the top and cross-sectional views respectively of the substrate shown in Figure 23A and Figure 23B after a first polymer layer was deposited and patterned.

[00095] Figure 25A and Figure 25B show the top and cross-sectional views respectively of the substrate shown in Figure 24A and Figure 24B after a second conductive layer is deposited and patterned.

[00096] Figure 26A and Figure 26B show the top and cross-sectional views respectively of the substrate shown in Figure 25A and Figure 25B after a second polymer layer was deposited and patterned; the via holes on the first polymer layer remain open so that the sacrificial layer can be etched.

[00097] Figure 27A and Figure 27B show the top and cross-sectional views respectively of the substrate shown in Figure 26A and Figure 26B after the sacrificial layer has been etched in a solvent. The remaining structure is a CMLIT with a cavity filled with air.

[00098] Figure 28A and Figure 28B show the top and cross-sectional views respectively of the substrate shown in Figure 27A and Figure 27B after the assembly has been sealed by an encapsulation material deposited in a low-pressure chamber.

[00099] Figure 29A and Figure 29B show the top and cross-sectional views respectively of a substrate with multiple layers and prefabricated conductive vias according to a fourth embodiment.

[000100] Figure 30A and Figure 30B show the top and cross-sectional views respectively of a substrate shown in Figure 29A and Figure 29B after mechanically polishing the substrate, removing a portion of substrate layers and exposing the conductive area. [000101] Figure 31 A and Figure 31 B show the top and cross-sectional views respectively of the substrate shown in Figure 30A and Figure 30B after a sacrificial layer was deposited and patterned. This sacrificial layer will become the cavity of a polyCMUT cell.

[000102] Figure 32 A and Figure 32B show the top and cross-sectional views respectively of the substrate shown in Figure 31 A and Figure 31 B after a first polymer layer was deposited and patterned.

[000103] Figure 33A and Figure 33B show the top and cross-sectional views respectively of the substrate shown in Figure 32A and Figure 32B after a second conductive layer was deposited and patterned.

[000104] Figure 34A and Figure 34B show the top and cross-sectional views respectively of the substrate shown in Figure 33A and Figure 33B after a second polymer layer was deposited and patterned; the via holes on the first polymer layer remain open so that the sacrificial layer can be etched.

[000105] Figure 35A and Figure 35B show the top and cross-sectional views respectively of the substrate shown in Figure 34A and Figure 34B after the sacrificial layer has been etched in a solvent. The remaining structure is a CMLIT with a cavity filled with air.

[000106] Figure 36A and Figure 36B show the top and cross-sectional views respectively of the substrate shown in Figure 35A and Figure 35B after the assembly has been sealed by an encapsulation material deposited in a low-pressure chamber.

[000107] Figures 37A and 37B show the top and cross-sectional views respectively of a silicon-based CMLIT fabricated on a printed circuit board according to a fifth embodiment. The materials of the printed circuit board are capable of withstanding the process conditions for the deposition of silicon, polysilicon, silicon dioxide, and silicon nitride layers (above 400 °C). [000108] Figure 38A and Figure 38B respectively represent the front side and the back side of a substrate having a circular shape and a plurality of conductive vias, according to an example embodiment.

[000109] Figure 39A and Figure 39B show the top isometric and top plan views respectively of an example polyCMUT linear array fabricated from the substrate of Figures 38A and 38B.

[000110] Figure 40A and Figure 40B show the bottom isometric and bottom plan views respectively of the polyCMUT linear array of Figures 39A and 39B,.

[000111] Figure 41 shows the cross-sectional view of the polyCMUT linear array of Figures 39A and 39B.

[000112] Figure 42A and Figure 42B show the top isometric and bottom isometric view respectively of an example polyCMUT matrix array fabricated according to an example embodiment.

[000113] Figure 43A shows the top view of the polyCMUT matrix array of Figures 42A and 42B. The polyCMUTs were fabricated on a polished surface with embedded vias.

[000114] Figure 43B shows the detail A from Figure 43A showing a plurality of polyCMUT elements in a matrix array. The via holes are not visible.

[000115] Figure 44A shows the bottom view of the polyCMUT matrix array of Figures 42A and 42B.

[000116] Figure 44B shows the detail A from Figure 44A showing a plurality of conductive vias and annular rings.

[000117] Figure 45A shows the bottom view of a polyCMUT linear array fabricated according to an example embodiment. Figure 45A shows an electrical contact assembly mounted at the rear of the array with a plurality of electrical tracks. [000118] Figure 45B shows the detail A shown in Figure 45A. An optional electronic component (or a circuit containing electronic components, such as a bias tee) is mounted between the vias and the electrical contact assembly.

[000119] Figure 46A shows the top view of the polyCMUT linear array of Figure 45A showing a plurality of polyCMUT elements.

[000120] Figure 46B shows the cross-sectional view A-A’ from Figure 46A showing a plurality of buried areas. PolyCMUT elements are on the top section.

[000121] Figure 46C shows the bottom view of the polyCMUT linear array of Figure 46A showing a plurality of contact areas.

[000122] Figure 46D shows the detail B from Figure 46B, in which several layers of the substrate with embedded electronic components are illustrated.

[000123] Figure 47 shows an exploded view of a polyCMUT transducer assembly fabricated according to an example embodiment. An acoustic lens is mounted on top of a polyCMUT linear array and a contact assembly is mounted at the rear.

[000124] Figures 48A, 48B, and 48C show the cross-sectional view of a polyCMUT linear array fabricated according to an example embodiment with different thicknesses and their relative bending condition along at least one axis. A thinner substrate leads to a smaller of curvature.

[000125] Figures 49A and 49B are pictures of a substrate having a circular shape and a plurality of conductive vias.

[000126] Figure 50A shows the detail B shown in Figure 49B. The plurality of contact areas where an ordinary electrical header can be mounted are apparent in Figure 50A.

[000127] Figure 50B shows the detail C shown in Figure 50A. The individual annular rings and even the conductive vias are apparent in Figure 50B. [000128] Figure 51 shows the detail A from Figure 49A. In Figure 51 , a plurality of via holes that will connect to the top electrode in polyCMUT elements are apparent.

[000129] Figure 52A and Figure 52B show the measurement of the surface roughness of the substrate of Figures 49A and 49B before and after the substrate has been polished.

[000130] Figure 53A shows a circular substrate with several polyCMUT arrays fabricated on the top of the substrate of Figures 49A and 49B, according to an example embodiment.

[000131] Figure 53B shows several of the polyCMUT arrays of Figure 53A after the substrate was diced to mechanically separate the arrays in the substrate.

[000132] Figure 54A shows a linear polyCMUT array fabricated according to an example embodiment. A contact assembly was soldered at the bottom of the array.

[000133] Figure 54B shows the polyCMUT array from Figure 54A mounted on a test circuit board. The polyCMUT elements can be independently controlled using this test circuit.

[000134] Figure 55A shows the time-domain response obtained from the polyCMUT array from Figure 54B operating in water. The CMUT transducer has a short pulse characteristic.

[000135] Figure 55B shows the frequency domain response of Figure 55A using a Fast Fourier Transform (FFT).

[000136] Figure 56A shows the computer design of a substrate PCB having a circular shape and a plurality of conductive vias shown in the inset.

[000137] Figure 56B shows the rear view of the substrate of Figure 56A, showing a plurality of contact pads electrically coupled to the substrate’s conductive vias. [000138] Figure 57A shows the front view of a physical substrate PCB manufactured based on the design of Figure 56A and having a circular shape and a plurality of conductive vias. The protective solder mask layer acts as a planarization layer.

[000139] Figure 57B shows the front view of the substrate from Figure 57A after polishing the conductive and the planarization layers.

[000140] Figure 58A shows a picture obtained using a microscope of the polished substrate from Figure 57B, with the polished surface having a mirror-like finishing.

[000141] Figure 58B shows a zoomed-in view of the polished substrate from Figure 58A, showing the polished conductive material and the polished planarization layer.

[000142] Figure 59A shows a picture of a needle profilometer to measure the surface roughness of the substrate from Figure 57B.

[000143] Figure 59B shows the profilometer measurement along the longitudinal axis of the substrate from Figure 59A to measure the curvature or “bow” of the substrate.

[000144] Figure 59C shows the profilometer measurement along the longitudinal axis of the substrate from Figure 59B to measure the surface roughness of the polished conductive material and the planarization layer.

[000145] Figure 60A shows the profilometer measurement along the X and Y axes of a standard 100 mm prime-grade silicon wafer with an oxide layer to measure the curvature or “bow” of the substrate.

[000146] Figure 60B shows the profilometer measurement along the X and Y axes of the substrate from Figure 59A to measure the curvature or “bow” of the substrate.

[000147] Figure 61 A shows a short profilometer measurement along the X axis of the center region of a standard 100mm prime-grade silicon wafer with an oxide layer to measure the surface roughness of the substrate. [000148] Figure 61 B shows a short profilometer measurement along the X axis of the center region of the substrate from Figure 59A to measure the surface roughness of the substrate.

[000149] Figure 62A shows a short profilometer measurement along the X axis of the planarization layer region from Figure 59A to measure the surface roughness.

[000150] Figure 62B shows an even shorter profilometer measurement (relative to Figure 62A) along the X axis of the center region of the substrate from Figure 59A to measure the surface roughness of the substrate.

[000151] Figure 63 shows a table with the expected ringing effects for a substrate consisting of FR4. The expected ringing correlates with the thickness of the substrate.

[000152] Figure 64A and Figure 64B show cross-sectional views of an ultrasound assembly comprising polyCMUTs manufactured in accordance with an example embodiment.

[000153] Figures 65A, 65B, and 65C show a probe assembly that has a flexible polyCMUT array manufactured in accordance with an example embodiment at its bottom. The polyCMUT array is deflected inwards depending on the pressure in an inner chamber of the probe assembly.

[000154] Figures 66A, 66B, and 66C show a probe assembly that has a flexible polyCMUT array manufactured in accordance with an example embodiment at its bottom. The polyCMUT array is deflected inwards due to a deflection mechanism.

[000155] Figure 67 shows a polyCMUT linear array manufactured in accordance with an example embodiment containing two planar inductors embedded in its substrate. DETAILED DESCRIPTION

[000157] As used herein: a. An “annular ring” is the area of copper pad around a drilled and finished via. All around this via there is enough conductive material (such as copper) to form a solid connection between conductive traces and the via in a multilayer PCB. Therefore, the main purpose of an annular ring is to establish a good connection between a via and the conductive trace leading to the via. In some cases, a via can be created without the need of an annular ring, or the annular ring may be small enough to be comparable to the diameter of a via. An annular ring is a particular example of a conductive pad that is electrically connected to the via. b. A CMLIT “array” is a group of CMLIT elements (e.g., 128 elements) aligned side by side in a one-dimensional (1 -D) arrangement (a “1 -D array” or a “linear array”), multiple linear arrays located side by side (a “1.5-D array”), or a two-dimensional array (“2-D array”, also called a “matrix array”) of CMLIT elements in communication with each other in both dimensions of the array. All of these types of arrays are capable of communication (once connected or active) with user interfaces either by wired communication or wireless signals. c. A “CMLIT” is a capacitive micromachined ultrasonic transducer, and includes polyCMUTs and silicon-based CMUTs unless the context indicates otherwise. d. A CMLIT “cell” is a single CMLIT transducer having a single moving membrane. e. A CMLIT “element” is a group of CMLIT cells (typically, between 100 and 300 cells). A CMLIT element is typically the smallest grouping of CMUTs that is connected to a single electrical connection is electrically coupled (i.e. , actuating a signal along the single electrical connection correspondingly actuates all the CMLIT cells forming the CMLIT element). f. “Embedding” an electrode within a polymer layer means completely covering the electrode with the polymer, except for any electrical connections made with that electrode. These connections are formed before completely embedding the electrode within the polymer layer. g. “Patterning” a material means to selectively remove that material either directly (e.g., if it is photosensitive) or by using a masking layer (e.g., in the case of a LOR™ composition). h. The term “polymer-based capacitive micromachined ultrasonic transducer” (“poly-CMUT” or “polyCMUT”) means a layered ultrasonic device with a polymeric membrane containing an embedded upper electrode suspended above a cavity. Examples of a poly-CMUT are found in US Patent No. 10,598,362 by Gerardo, Rohling, and Cretu. Combined with forming a sufficiently thin CMUT cavity, this structure permits the CMUT to reach the MHz operative region without requiring unacceptably high operating voltages. “Poly-CMUT” elements may be formed by the methods disclosed in US Patent No. 10,598,362 by Cretu et al. or United States Patent No. 7,673,375 by Chang et al.

Used in the manufacture of the poly-CMUTs are a LOR™ lift-off resist composition comprising cyclopentanone, PGME, a polyaliphatic imide copolymer, and a proprietary dye (less than 2 percent of total volume) and a surfactant; and “SU-8”, an optically transparent polymer-based photoresist material that comprises bisphenol A Novolac™ epoxy dissolved in an organic solvent and comprises up to 10 weight percent triarylsulfonium/hexafluoroantimonate salt. The LOR™ composition and SU-8 photoresist and the corresponding SU-8 developer may be acquired from Kayaku Advanced Materials of Westborough, Massachusetts. i. “Substrate” means an underlying substance or layer upon which the poly- CMLIT devices are fabricated. Substrates can comprise a range of metallic materials (e.g., aluminum), non-metallic materials (e.g., ceramics, composite materials), semiconductors (e.g., silicon) and even polymer- based materials such as polyimide, Kapton™, plexiglass, or Lexan™. A substrate can also comprise optically transparent or semitransparent materials such as glass or Indium Tin Oxide (ITO). A substrate can be rigid, semi-rigid, or flexible. A substrate can also comprise combinations of the aforementioned options: for example, a piece of glass covered by a layer of indium tin oxide, or a piece of polyimide covered by a metallic layer. A substrate in the form of a PCB may be rigid, semi-rigid, moderately flexible (i.e., bendable only to a certain radius of curvature), or fully flexible (i.e., bendable until opposing portions of the PCB contact each other and prevent further bending). Fully flexible PCBs in particular may be manufactured using polyimide as a substrate, for example. j. A “via” in a substrate such as a PCB is an electrical interconnect that extends at least partially through a substrate. For example, a via may be an electrical conductive path created when a hole or opening is filled with conductive material. This via hole can connect two or more surfaces in a multi-layer substrate (for example, a PCB). Vias are typically created mechanically (by using drilling or laser ablation) or chemically (using abrasive materials to etch the substrate in a selective way). These holes can be later electroplated to create the electrically conductive path to form the via. A common material for electroplating is, in some embodiments, copper (Cu). If a hollow via (i.e., the hole for the via is not completely covered by a conductive material) is created, a filler may be conductive or non-conductive epoxy. This is a practice to avoid material contamination and to prevent particles from accumulating in the hole. Vias can be plugged- vias, capped vias, though-hole vias, blind vias, buried vias, staggered vias, or microvias. Vias may follow a non-linear path through substrate (/.e., vias need not be a direct vertical connection between the top and bottom layers of the substrate). For example, inner layers of a substrate may be interconnected using conductive traces to facilitate deviation from a linear via that extends linearly between a substrate’s top and bottom layers. k. “X-ray mammography” means the practice of using radiographic imaging of a breast of a patient to screen for breast cancer. Young women in particular have a high proportion of dense breast tissue. During the radiographic imaging, the dense breast tissue absorbs X-rays in a manner which is to some extent similar to potential tumor tissue, making it difficult to distinguish between dense breast tissue and potential tumor tissue. Poly-CMUT arrays are useful in association with x-ray mammography.

List of identifiers

[000158] For a quick reference, the table below shows the identifiers used in this document:

10 assembly

11 substrate

12 top side

13 bottom side

14 upper substrate layer

15 lower substrate layer

21 via

22 annular ring

23 substrate conductive material

24 substrate conductive area for bottom electrode

25 substrate conductive area for top electrode

26 substrate conductive contact area

27 substrate conductive track

30 polished substrate

31 polished via

32 polished annular ring

33 polished substrate conductive material

34 bottom electrode

35 polished conductive area for top electrode

36 polished upper substrate layer planarization layer planarization layer via hole polished planarization layer substrate first conductive material bottom electrode contact area for top electrode sacrificial material sacrificial etch channel sacrificial membrane area first polymer layer first polymer via hole second conductive material top electrode area top electrode interconnect second polymer layer second polymer membrane area air area encapsulation material vacuum area silicon-based material silicon-based material via hole polyCMUT element polyCMUT linear array polyCMUT matrix array polyCMUT array polyCMUT group of arrays wafer substrate wafer substrate front side wafer substrate back side electrical interconnection track electrical contact assembly electrical contact assembly connection electrical contact mating connection electrical test circuit board electrical interface board acoustic lens electronic component planar inductor transducer assembly probe assembly probe case passage inner chamber deflection mechanism 263 deflected distance

270 ultrasound wave

271 unfocused ultrasound beam

272 focused ultrasound beam

273 focal point

280 wireless signal

[000159] In this context, at least some embodiments focus on specific custom izations of poly-CMUT technology for clinical purposes as well as non-destructive testing of physical structures.

[000160] The figures for certain of the different embodiments as follows:

• Figures 1A - 9B are in respect of the fabrication procedure of polyCMUTs according to a first embodiment, where a PCB with pre-existing via holes is grinded and polished to obtain a surface roughness in the orders of a few nanometers or lower.

• Figures 10A - 19B are in respect of the fabrication procedure of polyCMUTs according to a second embodiment, where a PCB with pre-existing via holes is grinded and polished to obtain a surface roughness on the order of a few tens or hundreds of nanometers. A planarization layer is subsequently deposited to reduce the surface roughness down to a few nanometers or lower. This may be achieved, for instance, by spin-coating a layer of polymer on top.

• Figures 20A - 28B are in respect of the fabrication procedure of polyCMUTs according to a third embodiment, where a PCB with pre-existing via holes and a pre-existing bottom electrode is covered with a planarization layer. Then, the substrate is grinded and polished to obtain a surface roughness on the order of a few tens or hundreds of nanometers, exposing the polished surface of the bottom electrode.

• Figures 29A - 36B are in respect of the fabrication procedure of polyCMUTs according to a fourth embodiment, and involve a multi-layer PCB with more than two layers and pre-existing via holes accessible from the bottom side. The bottom electrode of the depicted polyCMUT is patterned in one of the inner layers, surrounded by subsequent layers of the same core material. Then, the substrate is grinded and polished to obtain a surface roughness on the order of a few tens or hundreds of nanometers, exposing the polished surface of the bottom electrode. There is no need to add a planarization layer since the core material surrounds and encapsulates the bottom electrode.

• Figures 37 A and 37B are in respect of the fabrication procedure of silicon-based CMUTs according to a fifth embodiment in which the silicon-based CMLIT is fabricated on a ceramic substrate.

[000161] In the first embodiment, exemplified in Figure 1A (top view) and Figure 1 B (cross-sectional view taken along line X-X’ of Figure 1A), the assembly 10 is comprised of a substrate 11 with an exposed top side 12, bottom side 13 and vias 21 manufactured in the substrate 11. The bottom side 13 has additional layers in some embodiments (not shown), including protective layers for the conductive vias or for the protection of the substrate 11 . The vias 21 and the annular rings 22 are also exposed. The diameter D2 of the annular ring 22 extends beyond the diameter D1 of the via 21 . In these figures, the vias 21 are shown completely filled for illustrative purposes. The surface roughness of the top side is a result of the manufacturing process of the vias 21 and the type of material used as the substrate 11 . The thickness TC of the substrate conductive material 23 used for the annular ring 22 is determined from the expected electrical current in the conductive material 23; a thicker layer will allow more electrical current to flow though conductive tracks. The thickness T1 of the substrate 11 is determined from manufacturing specifications.

[000162] Referring now to Figure 2A (top view) and Figure 2B (cross-sectional view along line X-X’ of Figure 2A), a portion of the top side 12 of the assembly 10 is removed by mechanical means (such as a grinder or polishing machine) or by chemical means (such as a solvent that etches both the substrate 11 and the conductive materials used in the vias 21 and annular rings 22). The thickness of the material removed is equal to or more than the thickness TC of the annular ring 22. The initial thickness T 1 of the substrate 11 is reduced to a thickness T2 after the material is removed. The result is an assembly 10 with a polished substrate 30 and polished vias 31 with a surface roughness of a few nanometers or lower. The surface roughness depends on the removal mechanism.

[000163] Referring now to Figure 3A (top view) and Figure 3B (cross-sectional view along line X-X’ of Figure 3A), a first electrically conductive material 101 is deposited on top of the polished substrate 30 and polished vias 31 . The first conductive material 101 can be patterned using lithography techniques such as lift-off or etching a blanket layer of conductive material. The first conductive material 101 in some embodiments is a layer of chromium, followed by a layer of gold, followed by another layer of chromium. This first conductive material 101 can be deposited using, in some embodiments, physical vapor deposition systems such as an electron-beam metal evaporator. The typical thickness of this first conductive material 101 is a few tens of nanometers (typically 100 nm) in some embodiments. The first conductive material 101 is patterned, here in geometrical shapes, to form a bottom electrode 102 and a contact area 103 for a top electrode. Although the bottom electrode 102 and the contact area 103 for the top electrode are made of the same first conductive material 101 , they are not electrically connected; and there are areas where the polished substrate 30 is still exposed. The bottom electrode 102 will become the bottom electrode in a polyCMUT cell. The contact area 103 for the top electrode will become the electrical connection for the top electrode in a polyCMUT cell.

[000164] Referring now to Figure 4A (top view) and Figure 4B (cross-sectional view taken along line X-X’ of Figure 4A), a sacrificial material 105 is deposited on top of the assembly 10, covering portions of the polished substrate 30 and the first conductive material 101. The sacrificial material 105 can be patterned using lithography techniques such as lift-off or etching a blanket layer of sacrificial material. The sacrificial material 105 is in some embodiments, but is not limited to, a layer of LOR™ lift-off resist, followed by a layer of positive photoresist, followed by patterning via wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). This layer of sacrificial material 105 can be directly deposited on flat or curved surfaces using spin or spray coating with a very controllable thickness. For example, the sacrificial material 105 can be deposited using lithography coating techniques (such as a spin coater). The typical thickness of this sacrificial material 105 ranges from, in some embodiments, a few tens of nanometers to a few hundreds of nanometers (typically 200 nm), and even a few micrometers in some applications. The sacrificial material 105 is patterned (in geometrical shapes) to form sacrificial etch channels 106 in contact with a sacrificial membrane area 107. The sacrificial membrane area 107 will become the cavity in a polyCMUT cell. Only the sacrificial membrane area 107 is visible in the X-X' cross sectional view of Figure 4B.

[000165] As shown in Figure 5A (top view) and Figure 5B (cross-sectional view along lie X-X’ of Figure 5A), a first polymer layer 110 is deposited on top of the assembly 10, covering portions of the polished substrate 30, the first conductive material 101 , and the sacrificial material 105. This first polymer layer 110 can be (but is not limited to) a UV-photosensitive material such as Sll-8 photoresist. The first polymer layer 110 can be patterned directly using a UV exposure system then patterned using, for example, wet etching with Sll-8 developer. This first polymer layer 110 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer. This first polymer layer 110 can be deposited using, in some embodiments, lithography coating techniques such as a spin coater. The typical thickness of this first polymer layer 110 ranges from (but is not limited to) a few tens of nanometers to a few micrometers. In at least some embodiments, it is 700 nm. The thickness of this first polymer layer 110 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages. The first polymer layer 110 is patterned (in geometrical shapes) to form a uniform layer with some first polymer via holes 111. A bottom portion of the first polymer layer 110 between the bottom electrode 102 and the contact area 103 for the top electrode is co-planar with the bottom electrode 102 and the contact area 103 for the top electrode. The first polymer via holes 111 directly contact some portion of the sacrificial etch channels 106 from the exterior. The first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent that allows the sacrificial membrane area 107 to become the cavity in a polyCMUT cell. The sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 5A. The first polymer layer 110 covers the unconnected region of polished substrate 30 and prevents short circuits between the bottom electrode 102 and the contact area 103 for the top electrode.

[000166] In Figure 6A (top view) and Figure 6B (cross-sectional view taken along line X-X’ of Figure 6A), a second conductive material 115 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and some portions of the contact area 103 for the top electrode. In some embodiments, the second conductive material 115 can be patterned using lithography techniques such as lift-off or etching a blanket layer of conductive material. The second conductive material 115 is, in at least some embodiments, a layer of titanium, covered by a layer of gold. This second conductive material 115 is deposited, in some embodiments, using physical vapor deposition systems such as a sputtering system for a conformal covering. The typical thickness of this second conductive material 115 is in some embodiments a few tens of nanometers (including, for example, up to 100 nm). The second conductive material 115 is patterned (in geometrical shapes) to form a top electrode area 116 and a top electrode interconnect 117. The second conductive material 115 is patterned in such a way to avoid any overlap with the first polymer via holes 111 and to avoid any electrical contact with the bottom electrode 102; generally, the second conductive material 115 is patterned so as not to create short circuits between the bottom and top electrodes of a polyCMUT cell. The second conductive material 115 is patterned in such a way to maintain an electrical contact with the contact area 103 for the top electrode; therefore, an electrical connection is formed between the second conductive material 115 and only one of the vias 21 , which in Figure 6B is the via 21 on the right-hand side. The top electrode interconnect 117 is used to create an electrical connection with adjacent polyCMUT cells (not shown), and to allow the creation of polyCMUT elements 201. There exists at least one connection point between the top electrode interconnect 117 and the contact area for top electrode 103. The second conductive layer 115 will become the top electrode in a polyCMUT cell. [000167] Referring now to Figure 7A (top view) and Figure 7B (a cross-sectional view taken along line X-X’ of Figure 7A), a second polymer layer 120 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and the second conductive material 115. This second polymer layer 120 can be, in some embodiments, a UV photosensitive material such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be patterned directly using a UV exposure system and then patterned using, for example, wet etching using SU-8 developer. This second polymer layer 120 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer. This second polymer layer 120 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this second polymer layer 120 ranges from, in some embodiments, a few hundreds of nanometers to a few tens of micrometers (typically 5 urn). The thickness of this second polymer layer 120 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages. The second polymer layer 120 is patterned (in geometrical shapes) to form a second polymer membrane area 121 that avoids sealing or plugging the first polymer via holes 111. This second polymer layer 120 can also uniformly cover the entire assembly 10 (not shown in Figure 7A or Figure 7B) except in the areas where the first polymer via holes 111 are located. One purpose of this second polymer layer 120 is to increase the overall thickness of the membrane in a polyCMUT cell and to be able to operate at relatively high frequencies, such as between 1 MHz to 10 MHz. The sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 7A.

[000168] In Figure 8A (top view) and Figure 8B (cross-sectional view taken along line X-X’ of Figure 8A), the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise removed (e.g., mechanically). In some embodiments, the sacrificial material can be removed using wet etching using solvents or dry etching using gases. When using wet etching, the assembly 10 is immersed in, in some embodiments, an aqueous solution comprising tetramethylammonium hydroxide (TMAH). Doing this dissolves the sacrificial material 105 without damaging or dissolving the rest of the materials (/.e., the first polymer layer 110, second conductive material 115, and second polymer layer 120). Once the sacrificial material 105 is dissolved (etched), the assembly 10 is transferred into a container filled with isopropanol (IPA); the IPA accordingly replaces the aqueous solution comprising TMAH. Finally, the assembly 10 is transferred into the chamber of a critical point drier system (CPD), where liquid carbon dioxide (CO2) enters the chamber and replaces the IPA; then this liquid CO2 transforms into gaseous CO2 when the pressure in the chamber is gradually reduced to atmospheric pressure Once the assembly 10 is taken out of the critical point drier system, the areas where the sacrificial material 105 used to be have been replaced by an air area 125. The air area 125 allows the membrane in a polyCMUT cell to move, but it may not be suitable for water-coupled operations due to the presence of the first polymer via holes 111.

[000169] Referring now to Figure 9A (top view) and Figure 9B (cross-sectional view taken along line X-X’ of Figure 9A), an encapsulation material 130 is uniformly coated over the entire assembly 10 covering portions of the polished substrate 30, the first conductive material 101 , the first polymer layer 110, the second conductive material 115, and the second polymer layer 120. The encapsulation material 130 may be, in some embodiments, Parylene C. In some embodiments, the encapsulation material 130 can be deposited using a low-pressure chamber (e.g., a vacuum). The encapsulation material 130 conformally coats the top side 12 of the assembly 10, and gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are sealed. The thickness of this encapsulation material 130 may be at least half of the thickness of the sacrificial material 105 to have a proper seal of the sacrificial etch channels 106. The bottom side 13 of the assembly 10 can be protected (using for instance peelable tape) to prevent the encapsulation material 130 from covering the annular rings 22. The areas where the air area 125 used to be are accordingly replaced by a vacuum area 131. The vacuum area 131 allows the membrane in a polyCMUT cell to move in liquid-coupled applications, such as biomedical ultrasound examination. The vacuum area 131 becomes the sealed cavity in a polyCMUT cell.

[000170] In another embodiment, as shown in Figure 10A (top view) and Figure 10B (cross-sectional view taken along line X-X’ of Figure 10A), the assembly 10 is comprised of a substrate 11 with an exposed top side 12 and bottom side 13 and vias 21 manufactured in the substrate 11. The bottom side 13 may have additional layers (not shown), which may comprise protective layers for the conductive vias 21 or for the protection of the substrate 10. The vias 21 and the annular rings 22 are exposed. Note that diameter D2 of the annular ring 22 extends beyond diameter D1 of the via

21 . In this figure, the vias 21 are shown completely filled for illustrative purposes. The surface roughness of the top side 12 depends on the manufacturing process of the vias 21 and on the type of material used as the substrate 11 . The thickness TC of the substrate conductive material 23 used for the annular ring 22 is determined from manufacturing specifications. The thickness T 1 of the substrate 11 is determined from manufacturing specifications.

[000171] In Figure 11 A (top view) and Figure 11 B (cross-sectional view taken along line X-X’ of Figure 11A), a portion of the top side 12 of the assembly 10 is removed by mechanical means (such as a grinder or polishing machine) or by chemical means (such as a solvent that etches both the substrate 11 and the conductive materials used in the vias 21 and annular rings 22). The thickness of the material removed is in at least some embodiments equal to or more than the thickness TC of the annular ring

22. The initial thickness T1 of the substrate 11 is reduced to a thickness T2 after the material is removed. The result in at least some embodiments is an assembly 10 with a front side comprising a polished substrate 30 and polished vias 31 with a surface roughness of a few nanometers or less. The surface roughness depends on the removal mechanism.

[000172] Referring now to Figure 12A (top view) and Figure 12B (cross-sectional view taken along line X-X’ of Figure 12A), a planarization layer 40 is deposited on top of the assembly 10, covering portions of the polished substrate 30 and portions of the polished vias 31. The planarization layer 40 can be, in some embodiments, a UV photosensitive material such as Sll-8 photoresist. In some embodiments, the planarization layer 40 can be patterned directly using a UV exposure system and then patterned using, for example, wet etching using SU-8 developer. This planarization layer 40 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer. This planarization layer 40 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this planarization layer 40 ranges from, in some embodiments, a few tens of nanometers to a few micrometers (typically 1 urn). The thickness of this planarization layer 40 is selected based on the surface roughness of the polished substrate 30. The purpose of this planarization layer is to decrease the surface roughness down to a few nanometers or lower. The planarization layer 40 is patterned to form a uniform layer with some planarization layer via holes 41 exposed to subsequent layers. The planarization layer via holes 41 allow electrical conductivity between the vias 21 and subsequent electrically conductive layers through which the vias 21 extend.

[000173] In Figure 13A (top view) and Figure 13B (cross-sectional view taken along line X-X’ of Figure 13A), a first electrically conductive material 101 is deposited on top of the planarization layer 40 and polished vias 31 . In some embodiments, the first conductive material 101 is patterned using lithography techniques such as lift-off or etching a blanket layer of conductive material. The first conductive material 101 may be, in some embodiments, a layer of chromium, followed by a layer of gold, followed by a layer of chromium. This first conductive material 101 can be deposited using, in some embodiments, physical vapor deposition systems such as a sputtering system. The typical thickness of this first conductive material 101 is, in some embodiments, a few tens of nanometers (typically 100 nm). The first conductive material 101 is patterned (in geometrical shapes) to form the bottom electrode 102 and a contact area 103 for the top electrode. Even though the bottom electrode 102 and the contact area 103 for the top electrode are made of the same first conductive material 101 , they are not electrically connected to each other; there accordingly exist areas where the planarization layer 40 is still exposed. The bottom electrode 102 will become the bottom electrode in a polyCMUT cell. The contact area 103 for the top electrode will become the electrical connection for the top electrode in a polyCMUT cell.

[000174] Referring now to Figure 14A (top view) and Figure 14B (cross-sectional view taken along line X-X’ of Figure 14A), a sacrificial material 105 is deposited on top of the assembly 10, covering portions of the planarization layer 40 and the first conductive material 101. In some embodiments, the sacrificial material 105 can be patterned using lithography techniques such as lift-off or etching a blanket layer of sacrificial material. The sacrificial material 105 may be, in some embodiments, a layer of LOR™ lift-off resist, followed by a layer of, in some embodiments, positive photoresist. The sacrificial material 105 is then patterned using, for example, wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). This sacrificial material 105 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this sacrificial material 105 ranges from, in some embodiments, a few tens of nanometers to a few hundreds of nanometers (typically 200 nm), and even a few micrometers in some applications. The sacrificial material 105 is patterned (in geometrical shapes) to form sacrificial etch channels 106 in contact with a sacrificial membrane area 107. The sacrificial membrane area 107 will become the cavity in a polyCMUT cell. Only the sacrificial membrane area 107 is visible in the cross sectional view of Figure 14B.

[000175] In Figure 15A (top view) and Figure 15B (cross-sectional view taken along line X-X’ of Figure 15A), a first polymer layer 110 is deposited on top of the assembly 10, covering portions of the planarization layer 40, the first conductive material 101 , and the sacrificial material 105. This first polymer layer 110 can be, in some embodiments, a UV photosensitive material such as Sll-8 photoresist. In some embodiments, the first polymer layer 110 can be patterned directly using a UV exposure system then patterned via (not limited to) wet etching using SU-8 developer. This first polymer layer 110 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer. This first polymer layer 110 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this first polymer layer 110 ranges from, in some embodiments, a few tens of nanometers to a few micrometers (typically 700 nm). The thickness of this first polymer layer 110 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages. The first polymer layer 110 is patterned (in geometrical shapes) to form a uniform layer with some first polymer via holes 111. The first polymer via holes 111 create a direct contact to some portion of the sacrificial etch channels 106 from the exterior. The first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent that allows the sacrificial membrane area 107 to become the cavity in a polyCMUT cell. The sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 15A. The first polymer layer 110 covers the unconnected region of the planarization layer 40 and prevents short circuits between the bottom electrode 102 and the contact area 103 for the top electrode.

[000176] In Figure 16A (top view) and Figure 16B (cross-sectional view taken along line X-X’ of Figure 16A), a second conductive material 115 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and some portions of the contact area 103 for the top electrode. In some embodiments, the second conductive material 115 can be patterned using lithography techniques such as lift-off or etching a blanket layer of conductive material. The second conductive material 115 may be, in some embodiments, a layer of titanium, followed by a layer of gold. This second conductive material 115 can be deposited using, in some embodiments, physical vapor deposition systems (such as a sputtering system) for a conformal covering. The thickness of this second conductive material 115 is, in some embodiments, a few tens of nanometers (typically 100 nm). The second conductive material 115 is patterned (in geometrical shapes) to form a top electrode area 116 and a top electrode interconnect 117. The second conductive material 115 is patterned in such a way to avoid any overlap with the first polymer via holes 111. The second conductive material 115 is also patterned in such a way to avoid any electrical contact with the bottom electrode 102 so as not to create short circuits between the bottom and top electrodes of a polyCMUT cell. The second conductive material 115 is also patterned in such a way to maintain an electrical contact with the contact area 103 for the top electrode; therefore, an electrical connection is formed between the second conductive material 115 and only one of the vias 21 , which in Figure 20 is the via 21 on the right-hand side. The top electrode interconnect 117 is used to create an electrical connection with adjacent polyCMUT cells (not shown), and to allow the creation of polyCMUT elements 201 . There exists at least one connection point between the top electrode interconnect 117 and the contact area 103 for the top electrode. The second conductive layer 115 will become the top electrode in a polyCMUT cell.

[000177] In Figure 17A (top view) and Figure 17B (cross-sectional view taken along line X-X’ of Figure 17A), a second polymer layer 120 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and the second conductive material 115. This second polymer layer 120 can be, in some embodiments, a UV photosensitive material such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be patterned directly using a UV exposure system then patterned via (not limited to) wet etching using SU-8 developer. This second polymer layer 120 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer. This second polymer layer 120 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this second polymer layer 120 ranges from, in some embodiments, a few hundreds of nanometers to a few tens of micrometers (typically 5 urn). The thickness of this second polymer layer 120 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages. The second polymer layer 120 is patterned (in geometrical shapes) to form a second polymer membrane area 121 that avoids sealing or plugging the first polymer via holes 111. This second polymer layer 120 can also uniformly cover the entire assembly 10 (not shown in Figure 17A or Figure 17B) except in the areas where the first polymer via holes 111 are located. One purpose of this second polymer layer 120 is to increase the overall thickness of the membrane in a polyCMUT cell so as to increase its maximum operating frequency. The sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 17A.

[000178] Referring now to Figure 18A (top view) and Figure 18B (cross-sectional view taken along line X-X’ of Figure 18A), the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane area 107) is etched, dissolved or removed. In some embodiments, the sacrificial material 105 can be removed with wet etching using solvents or dry etching using gases. When using wet etching, the assembly 10 is immersed, in some embodiments, in an aqueous solution containing tetramethylammonium hydroxide (TMAH) thereby dissolving the sacrificial material 105 without damaging or dissolving the rest of the materials (i.e., the first polymer layer 110, second conductive material 115, and second polymer layer 120). Once the sacrificial material 105 is dissolved, the assembly 10 is transferred into a container filled with isopropanol (IPA); the IPA replaces the aqueous solution containing TMAH. Finally, the assembly 10 is transferred into the chamber of a critical point drier system (CPD), where liquid carbon dioxide (CO2) enters the chamber and replaces the IPA; then this liquid CO2 transforms into gaseous CO2 when the pressure in the chamber is gradually reduced to atmospheric pressure. Once the assembly is taken out of the critical point drier system, the areas where the sacrificial material 105 used to be have been replaced by an air area 125. The air area 125 allows the membrane in a polyCMUT cell to move, but it may not be suitable for water-coupled operations due to the presence of the first polymer via holes 111.

[000179] Referring now to Figure 19A (top view) and Figure 19B (cross-sectional view taken along line X-X’ of Figure 19A), an encapsulation material 130 is uniformly coated over the entire assembly 10 thereby covering portions of the planarization layer 40, the first conductive material 101 , the first polymer layer 110, the second conductive material 115, and the second polymer layer 120. The encapsulation material 130 may be, in some embodiments, Parylene C, and in some embodiments, be deposited using a low-pressure chamber (to be considered vacuum). The encapsulation material 130 conformally coats the top side 12 of the assembly 10, and it gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are plugged. The thickness of this encapsulation material 130 is in at least some embodiments half of the thickness of the sacrificial material 105 to help ensure a proper seal of the sacrificial etch channels 106. The bottom side 13 of the assembly 10 can be protected (using for instance, peelable tape) to prevent the encapsulation material 130 from covering the annular rings 22. The areas where the air area 125 used to be are also replaced by a vacuum area 131. The vacuum area 131 allows the membrane in a polyCMUT cell to move in liquid-coupled applications, such as biomedical ultrasound examinations. The vacuum area 131 becomes the sealed cavity in a polyCMUT cell. [000180] In a third embodiment, as shown in Figure 20A (top view) and Figure 20B (cross-sectional view taken along line X-X’ of Figure 20A), the assembly 10 is comprised of a substrate 11 with an exposed top side 12 and bottom side 13 and vias 21 manufactured into the substrate 11. The bottom side 13 has additional layers in some embodiments (not shown) that include protective layers for the conductive vias 21 or for the protection of the substrate 11 . The vias 21 and the annular rings 22 are exposed. The diameter D2 of the annular ring 22 extends beyond the diameter D1 of the via 21. In this figure, the vias 21 are shown completely filled for illustrative purposes. The surface roughness of the top side 12 depends on the manufacturing process of the vias 21 and on the type of material used as substrate 11 . The thickness TC of the substrate conductive material 23 used for the annular ring 22 is determined from manufacturing specifications. The thickness T1 of the substrate 11 is determined from manufacturing specifications. In the assembly 10, the substrate conductive material 23 has been patterned to obtain a substrate conductive area 24 for the bottom electrode and a substrate conductive area 25 for the top electrode. In some embodiments, the substrate conductive material 23 is patterned during the fabrication of the assembly 10 using lithography techniques such as masking and etching like those used in a PCB manufacturing facility. The via 21 makes a direct electrical connection between the substrate conductive area 24 for the bottom electrode on the top side 12 and the annular ring 22 on the bottom side 13. The via 21 also makes a direct electrical connection between the substrate conductive area 25 for the top electrode on the top side 12 and the annular ring 22 on the bottom side 13. Even though the substrate conductive area 24 for the bottom electrode and the substrate conductive area 25 for the top electrode are made of the same substrate conductive material 23, they are not electrically connected with each other.

[000181] In Figure 21 A (top view) and Figure 21 B (cross-sectional view taken along line X-X’ of Figure 21 A), a planarization layer 40 is deposited on top of the assembly 10, covering portions of the substrate 11 , portions of the substrate conductive area 24 for the bottom electrode, and portions of the substrate conductive area 25 for the top electrode. The planarization layer 40 can be, in some embodiments, an epoxy resin such as Epotek-302 ^TM or Epotek-302-3M ^TM . This planarization layer 40 can be deposited using, in some embodiments, lithography coating techniques, such as a spin coater. The thickness of this planarization layer 40 is in at least some embodiments equal to or greater than the thickness TC of the substrate conductive material 23. The planarization layer 40 conformally covers all the sides of the substrate conductive material 23 that are not in contact with the substrate 11 . An optional degassing stage can be used to remove any air bubbles that might become trapped during the deposition of this planarization layer 40. The purpose of this planarization layer 40 is to fill the exposed areas on the top side 12 of the substrate 11 that are not already covered by the substrate conductive material 23.

[000182] Referring now to Figure 22 A (top view) and Figure 22B (cross-sectional view taken along line X-X’ of Figure 22A), a portion of the top side 12 of the assembly 10 is removed by mechanical means (such as a grinder or polishing machine) or by chemical means (such as a solvent that etches both the planarization layer 40 and the substrate conductive material 23). After the removal of the material, the thickness TCP of the polished substrate conductive material 33 is smaller than the original thickness TC of the substrate conductive material 23. The result is an assembly 10 with a polished substrate conductive material 33 and a polished planarization layer 50 with a surface roughness of a few nanometers or even much less. The surface roughness depends on the removal mechanism. After this polishing step, the thickness of the polished substrate conductive material 33 and the polished planarization layer 50 have the same thickness TCP. Maintaining a flat and leveled surface is important for the upcoming fabrication steps for creating polyCMUT cells and eventually polyCMUT elements 201 and polyCMUT arrays 204. A portion of the polished planarization layer 50 between a polished conductive area which acts as the bottom electrode 34 and a polished conductive area 35 for the top electrode is co-planar with the bottom electrode 34 and the conductive area 35.

[000183] In Figure 23A (top view) and Figure 23B (cross-sectional view taken along line X-X’ of Figure 23A), a sacrificial material 105 is deposited on top of the assembly 10, covering portions of the polished planarization layer 50 and the polished substrate conductive material 33. In some embodiments, the sacrificial material 105 can be patterned using lithography techniques such as lift-off or etching a blanket layer of sacrificial material. The sacrificial material 105 may be, in some embodiments, a layer of LOR™ lift-off resist, followed by a layer of, in some embodiments, positive photoresist, which is then patterned via wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). This sacrificial material 105 can be deposited using, in some embodiments, lithography coating techniques such as a spin coater. The typical thickness of this sacrificial material 105 ranges from, in some embodiments, a few tens of nanometers to a few hundreds of nanometers (typically 200 nm), and even a few micrometers in some applications. The sacrificial material 105 is patterned in geometrical shapes to form sacrificial etch channels 106 in contact with a sacrificial membrane area 107. The sacrificial membrane area 107 will become the cavity in a polyCMUT cell. Only the sacrificial membrane area 107 is visible in the cross-sectional view in Figure 23B.

[000184] Referring now to Figure 24A (top view) and Figure 24B (cross-sectional view taken along line X-X’ of Figure 24), a first polymer layer 110 is deposited on top of the assembly 10, covering portions of the polished planarization layer 50, the polished substrate conductive material 33, and the sacrificial material 105. This first polymer layer 110 can be, in some embodiments, a UV photosensitive material such as Sil-8 photoresist. In some embodiments, the first polymer layer 110 can be patterned directly using a UV exposure system and then patterned using, in some embodiments, wet etching with SU-8 developer. This first polymer layer 110 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer. This first polymer layer 110 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this first polymer layer 110 ranges from, in some embodiments, a few tens of nanometers to a few micrometers (typically 700 nm). The thickness of this first polymer layer 110 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages, ranging from 10 V - 100 V. The first polymer layer 110 is patterned (in geometrical shapes) to form a uniform layer with some first polymer via holes 111. The first polymer via holes 111 create a direct connection to some portions of the sacrificial etch channels 106 from the exterior. The first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent that allows the sacrificial membrane area 107 to become the cavity in a polyCMUT cell. The sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 24A. The fist polymer layer 110 covers the unconnected region of the polished planarization layer 50 and prevents short circuits between the polished conductive area that acts as the bottom electrode 34 and the polished conductive area 35 for the top electrode.

[000185] In Figure 25A (top view) and Figure 25B (cross-sectional view taken along line X-X’ of Figure 25A), a second conductive material 115 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and some portions of the polished conductive area for top electrode 35. In some embodiments, the second conductive material 115 can be patterned using lithography techniques such as lift-off or etching a blanket layer of conductive material. The second conductive material 115 may be, in some embodiments, a layer of titanium, followed by a layer of gold. This second conductive material 115 can be deposited using, in some embodiments, physical vapor deposition systems (such as a sputtering system) for a conformal covering. The typical thickness of this second conductive material 115 is, in some embodiments, a few tens of nanometers (typically 100 nm). The second conductive material 115 is patterned (in geometrical shapes) to form a top electrode area 116 and a top electrode interconnect 117. The second conductive material 115 is patterned in such a way to avoid any overlap with the first polymer via holes 111. The second conductive material 115 is patterned in such a way to avoid any electrical contact with the polished conductive area that acts as the bottom electrode 34 to avoid short circuiting the bottom and top electrodes of a polyCMUT cell. The second conductive material 115 is patterned in such a way to maintain an electrical contact with the polished conductive area 35 for the top electrode; therefore, an electrical connection is formed between the second conductive material 115 and only one of the vias 21 , which in Figure 25B is the via 21 on the right-hand side. The top electrode interconnect 117 is used to create an electrical connection with adjacent polyCMUT cells (not shown), and to allow the creation of polyCMUT elements 201. There exists at least one connection point between the top electrode interconnect 117 and the polished conductive area 35 for the top electrode. The second conductive layer 115 will become the top electrode in a polyCMUT cell.

[000186] Referring now to Figure 26A (top view) and Figure 26B (cross-sectional view taken along line X-X’ of Figure 26A), a second polymer layer 120 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and the second conductive material 115. This second polymer layer 120 can be, in some embodiments, a UV photosensitive material such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be patterned directly using a UV exposure system and then patterned using, for example, wet etching using SU-8 developer. This second polymer layer 120 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer. This second polymer layer 120 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this second polymer layer 120 ranges from, in some embodiments, a few hundreds of nanometers to a few tens of micrometers (typically 5 urn). The thickness of this second polymer layer 120 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages. The second polymer layer 120 is patterned (in geometrical shapes) to form a second polymer membrane area 121 that avoids sealing or plugging the first polymer via holes 111. This second polymer layer 120 can also uniformly cover the entire assembly 10 (not shown in Figure 26A or Figure 26B) except in the areas where the first polymer via holes 111 are located. The purpose of this second polymer layer 120 is to increase the overall thickness of the membrane in a polyCMUT cell so as to be able to operate at frequencies between 1 MHz and 10 MHz.. The sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 26A.

[000187] In Figure 27A (top view) and Figure 27B (cross-sectional view taken along line X-X’ of Figure 27A), the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise removed (e.g., mechanically). In some embodiments, the sacrificial material 105 can be removed with wet etching using solvents or dry etching using gases. When using wet etching, the assembly 10 is immersed in, in some embodiments, an aqueous solution containing tetramethylammonium hydroxide (TMAH) where the sacrificial material 105 is dissolved without damaging or dissolving the rest of the materials (i.e., the first polymer layer 110, second conductive material 115, and second polymer layer 120). Once the sacrificial material 105 is dissolved, the assembly is transferred into a container filled with isopropanol (IPA); the IPA replaces the aqueous solution containing TMAH. Finally, the assembly 10 is transferred into the chamber of a critical point drier system (CPD), where liquid carbon dioxide (CO2) enters the chamber at high pressures and replaces the IPA; then this liquid CO2 transforms into gaseous CO2 when the pressure in the chamber is gradually reduced to atmospheric pressure. Once the assembly 10 is taken out of the critical point drier system, the areas where the sacrificial material 105 used to be are now replaced by an air area 125. The air area 125 allows the membrane in a polyCMUT cell to move, but it is not suitable for water-coupled operations due to the presence of the first polymer via holes 111.

[000188] In Figure 28A (top view) and Figure 28B (cross-sectional view taken along line X-X’ of Figure 28A), an encapsulation material 130 is uniformly coated over the entire assembly 10, thereby covering portions of the polished planarization layer 50, the polished substrate conductive material 33, the first polymer layer 110, the second conductive material 115, and the second polymer layer 120. The encapsulation material 130 may be, in some embodiments, Parylene C. In embodiments, the encapsulation material 130 can be deposited using a low-pressure chamber, such as in a vacuum. The encapsulation material 130 conformally coats the top side 12 of the assembly 10, and it gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are sealed. The thickness of this encapsulation material 130 is in at least some embodiments at least half of the thickness of the sacrificial material 105 so as to have a proper seal of the sacrificial etch channels 106. The bottom side 13 of the assembly 10 can be protected (using for instance peelable tape) to prevent the encapsulation material 130 from covering the annular rings 22. The areas where the air area 125 was is replaced by a vacuum area 131 . The vacuum area 131 allows the membrane in a polyCMUT cell to move in liquid-coupled applications, such as biomedical ultrasound examination. The vacuum area 131 becomes the sealed cavity in a polyCMUT cell.

[000189] In a fourth embodiment, as shown in Figure 29A (top view) and Figure 29B (cross-sectional view taken along line X-X’ of Figure 29A), the assembly 10 is comprised of a substrate 11 bonded and accordingly adhered to an upper substrate layer 14. This upper substrate layer 14 is made of the same material as the substrate 11. The materials for the substrate 11 and the upper substrate layer 14 typically comprise, in some embodiments, glass-reinforced epoxy laminate material (commonly known as “FR4”) or hydrocarbon ceramic laminates (commonly known as “Rogers material”). The substrate 11 and the upper substrate layer 14 are typically bonded in vacuum at high temperatures to avoid any air bubbles or voids in between. The assembly 10 may have an additional lower substrate layer 15 (not shown in Figure 29A or 29B) bonded on the bottom side 13 of the substrate 10. This optional lower substrate layer 15 has the same physical properties as the upper substrate layer 14. The optional lower substrate layer 15 may have vias 21 to maintain an electrical connection with the substrate conductive material 23. The bottom side 13 of the substrate 11 may have additional layers (not shown) that may include protective layers for the conductive vias 21 or for the protection of the substrate 11. The vias 21 and the annular rings 22 are exposed. The diameter D2 of the annular ring 22 extends beyond the diameter D1 of the via 21. The vias 21 are shown completely filled for illustrative purposes. The thickness TC of the substrate conductive material 23 used for the annular ring 22 is determined from manufacturing specifications. The thicknesses T1 of the substrate 11 and T3 of the upper substrate layer 14 are determined from manufacturing specifications; typically, T3 is larger than T1. In the assembly 10, the substrate conductive material 23 between the substrate 11 and the upper substrate layer 14 has been patterned to obtain a substrate conductive area 24 for the bottom electrode and a substrate conductive area 25 for the top electrode 25 (shown as dashed lines in Figure 29A). In some embodiments, the substrate conductive material 23 is patterned during the fabrication of the assembly 10 using lithography techniques such as masking and etching like those used in a PCB manufacturing facility. The via 21 makes a direct electrical connection between the substrate conductive area 24 for the bottom electrode on the top side 12 and the annular ring 22 on the bottom side 13. The via 21 makes a direct electrical connection between the substrate conductive area 25 for the top electrode and the annular ring 22 on the bottom side 13. Even though the substrate conductive area 24 for the bottom electrode and the substrate conductive area 25 for the top electrode are made of the same substrate conductive material 23, they are not electrically connected to each other.

[000190] Referring now to Figure 30A (top view) and Figure 30B (cross-sectional view taken along line X-X’ of Figure 30A), a portion of the assembly 10 is removed by mechanical means (such as a grinder or polishing machine) or by chemical means (such as a solvent that etches both the upper substrate layer 14 and the substrate conductive material 23). After the removal of the material, the thickness TCP of the polished substrate conductive material 33 is smaller than the original thickness TC of the substrate conductive material 23. The result is an assembly 10 with a polished substrate conductive material 33 and a polished upper substrate layer 36 with a surface roughness of a few nanometers or lower. The surface roughness depends on the removal mechanism. After this polishing step, the thickness of the polished substrate conductive material 33 and the polished upper substrate layer 36 have the same thickness TCP. Fabrication in accordance with this depicted embodiments can be done without the deposition of a planarization layer 40, which is discussed above in respect of Figure 21 A. Maintaining a flat and level surface is important for the upcoming fabrication steps for crating polyCMUT cells and eventually polyCMUT elements 201 and polyCMUT arrays 204. A portion of the PCB itself (i.e. , the polished upper substrate layer 36) between a polished conductive area that acts as the bottom electrode 34 and a polished conductive area 35 for the top electrode is co-planar with the bottom electrode 34 and the conductive area 35.

[000191] In Figure 31 A (top view) and Figure 31 B (cross-sectional view taken along line X-X’ of Figure 31 A), a sacrificial material 105 is deposited on top of the assembly 10, covering portions of the polished upper substrate layer 36 and the polished substrate conductive material 33. In some embodiments, the sacrificial material 105 can be patterned using lithography techniques such as lift-off or etching a blanket layer of sacrificial material. The sacrificial material 105 may be, in some embodiments, a layer of LOR™ lift-off resist, followed by a layer of, in some embodiments, positive photoresist, which is then patterned with, for example, wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). This sacrificial material 105 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this sacrificial material 105 ranges from, in some embodiments, a few tens of nanometers to a few hundreds of nanometers (typically 200 nm), and even a few micrometers in some applications. The sacrificial material 105 is patterned (in geometrical shapes) to form sacrificial etch channels 106 in contact with a sacrificial membrane area 107. The sacrificial membrane area 107 will become the cavity in a polyCMUT cell. Only the sacrificial membrane area 107 is visible in Figure 31 B.

[000192] Referring now to Figure 32 A (top view) and Figure 32B (cross-sectional view taken along line X-X’ of Figure 32A), a first polymer layer 110 is deposited on top of the assembly 10, covering portions of the polished upper substrate layer 36, the polished substrate conductive material 33, and the sacrificial material 105. This first polymer layer 110 can be, in some embodiments, a UV photosensitive material such as Sil-8 photoresist. In some embodiments, the first polymer layer 110 can be patterned directly using a UV exposure system and then patterned with, for example, wet etching using SU-8 developer. This first polymer layer 110 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer layer. This first polymer layer 110 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this first polymer layer 110 ranges from, in some embodiments, a few tens of nanometers to a few micrometers (typically 700 nm). The thickness of this first polymer layer 110 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages between 10 V and 100 V. The first polymer layer 110 is patterned (in geometrical shapes) to form a uniform layer with some first polymer via holes 111. The first polymer via holes 111 create a direct connection to some portions of the sacrificial etch channels 106 from the exterior. The first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent that will allow the sacrificial membrane area 107 to become the cavity in a polyCMUT cell. The sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 32A. The fist polymer layer 110 covers the electrically unconnected region of the polished upper substrate layer 36 and prevents short circuits between the polished conductive area that acts as the bottom electrode 34 and the polished conductive area 35 for the top electrode.

[000193] Referring now to Figure 33A (top view) and Figure 33B (cross-sectional view taken along line X-X’ of Figure 33A), a second conductive material 115 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and some portions of the polished conductive area 35 for the top electrode. In some embodiments, the second conductive material 115 can be patterned using lithography techniques such as lift-off or etching a blanket layer of conductive material. The second conductive material 115 may be, in some embodiments, a layer of titanium, followed by a layer of gold. This second conductive material 115 can be deposited using, in some embodiments, physical vapor deposition systems (such as a sputtering system) for a conformal covering. The typical thickness of this second conductive material 115 is, in some embodiments, a few to several tens of nanometers (typically 100 nm). The second conductive material 115 is patterned (in geometrical shapes) to form a top electrode area 116 and a top electrode interconnect 117. The second conductive material 115 is patterned in such a way to avoid any overlap with the first polymer via holes 111. The second conductive material 115 is patterned in such a way to avoid any electrical contact with the polished conductive area that acts as the bottom electrode 34; otherwise, it would create short circuits between the bottom and top electrodes of a polyCMUT cell. The second conductive material 115 is patterned in such a way to maintain an electrical contact with the polished conductive area 35 for the top electrode; therefore, an electrical connection is formed between the second conductive material 115 and only one of the vias 21 , which in Figure 25B is the via 21 on the right-hand side. The top electrode interconnect 117 is used to create an electrical connection with adjacent polyCMUT cells (not shown), and to allow the creation of polyCMUT elements 201. There exists at least one connection point between the top electrode interconnect 117 and the polished conductive area 35 for the top electrode. The second conductive layer 115 will become the top electrode in a polyCMUT cell.

[000194] Referring now to Figure 34A (top view) and Figure 34B (cross-sectional view taken along line X-X’ of Figure 34A), a second polymer layer 120 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and the second conductive material 115. This second polymer layer 120 can be, in some embodiments, a UV photosensitive material such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be patterned directly using a UV exposure system then patterned with, for example, wet etching using SU-8 developer. This second polymer layer 120 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer. This second polymer layer 120 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater). The typical thickness of this second polymer layer 120 ranges from, in some embodiments, a few hundreds of nanometers to a few tens of micrometers (typically 5 urn). The thickness of this second polymer layer 120 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages, between 10 V and 100 V. The second polymer layer 120 is patterned (in geometrical shapes) to form a second polymer membrane area 121 that avoids sealing or plugging the first polymer via holes 111. This second polymer layer 120 can also uniformly cover the entire assembly 10 (not shown in Figure 34A or Figure 34B) except in the areas where the first polymer via holes 111 are located. The purpose of this second polymer layer 120 is to increase the overall thickness of the membrane in a polyCMUT cell and to be able to reach a desired frequency between 1 MHz and 10 MHz. The sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 34A.

[000195] Referring now to Figure 35A (top view) and Figure 35B (cross-sectional view taken along line X-X’ of Figure 35A), the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise removed (e.g., mechanically). In some embodiments, the sacrificial material can be removed with, in some embodiments, wet etching using solvents or dry etching using gases. When using wet etching, the assembly 10 is immersed in, in some embodiments, an aqueous solution containing tetramethylammonium hydroxide (TMAH), where the sacrificial material 105 is dissolved without damaging or dissolving the rest of the materials (i.e., the first polymer layer 110, second conductive material 115, and second polymer layer 120). Once the sacrificial material 105 is dissolved, the assembly is transferred into a container filled with isopropanol (IPA); the IPA replaces the aqueous solution containing TMAH. Finally, the assembly 10 is transferred into the chamber of a critical point drier system (CPD), where liquid carbon dioxide (CO2) enters the chamber at high pressures and replaces the IPA; then this liquid CO2 transforms into gaseous CO2 when the pressure in the chamber is gradually reduced to atmospheric pressure. Once the assembly 10 is taken out of the critical point drier system, the areas where the sacrificial material 105 used to be are replaced by an air area 125. The air area 125 allows the membrane in a polyCMUT cell to move, but it may not be suitable for water-coupled operations due to the presence of the first polymer via holes 111.

[000196] Referring now to Figure 36A (top view) and Figure 36B (cross-sectional view taken along line X-X’ of Figure 36A), an encapsulation material 130 is uniformly coated over the entire assembly 10, thereby covering portions of the polished upper substrate layer 36, the polished substrate conductive material 33, the first polymer layer 110, the second conductive material 115, and the second polymer layer 120. The encapsulation material 130 may be, in some embodiments, Parylene C. In some embodiments, the encapsulation material 130 can be deposited using a low-pressure chamber, which may operate as a vacuum. The encapsulation material 130 conformally coats the top side of the assembly 10, and it gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are plugged and thereby sealed. The thickness of this encapsulation material 130 is in at least some embodiments at least half of the thickness of the sacrificial material 105 to have a proper seal of the sacrificial etch channels 106. The bottom side 13 of the assembly 10 can be protected (using for instance peelable tape) to prevent the encapsulation material 130 from covering the annular rings 22. The areas where the air area 125 were are replaced by a vacuum area 131 . The vacuum area 131 allows the membrane in a polyCMUT cell to move in liquid-coupled applications, such as biomedical ultrasound examination. The vacuum area 131 becomes the sealed cavity in a polyCMUT cell.

[000197] The solvents used for wet etching in the first through fourth embodiments depicted in Figures 1A to 37B are selected to be chemically compatible with the substrate 11 and the other materials deposited on the substrate, such as the various polymer layers 110,120 and the conductive material 115 used for electrodes. I.e. , the solvent is selected to etch away the sacrificial material 105 without dissolving or damaging the substrate 11 and those other materials. Example suitable solvents used for wet etching comprise SU-8 developer of which the predominant ingredient is 1- methoxy-2-propanol acetate and tetramethylammonium hydroxide (TMAH). Other suitable solvents may comprise 1 -methoxy-2-propanol acetate alone or when part of another composition that is not SU-8 developer, acetone, and isopropanol (IPA).

[000198] Referring now to Figure 37A (top view) and Figure 37B (cross-sectional view taken along line X-X’ of Figure 37A), an encapsulation material 130 is uniformly coated over the entire assembly 10, thereby covering portions of the polished upper substrate layer 36, the polished substrate conductive material 33, the silicon-based material 110, and the second conductive material 115. The encapsulation material 130 may be, in some embodiments, silicon nitride, silicon dioxide, or polysilicon. In some embodiments, the encapsulation material 130 can be deposited using a low- pressure chamber that may operate as a vacuum. The encapsulation material 130 conformally coats the top side of the assembly 10, enters the silicon-based material via holes 141 , and gradually accumulates up the inner walls of the sacrificial etch channels 106 until they are plugged and thereby sealed. The thickness of this encapsulation material 130 is in at least some embodiments at least half of the thickness of the sacrificial material 105 so as to enable a proper seal of the sacrificial etch channels 106. The bottom side 13 of the assembly 10 can be protected (using for instance a masking layer) to prevent the encapsulation material 130 from covering the annular rings 22. The areas where the air area 125 used to be are replaced by a vacuum area 131. The vacuum area 131 allows the membrane in a silicon-based CMLIT cell to move in liquid-coupled applications, such as a biomedical ultrasound examination. The vacuum area 131 becomes the sealed cavity in a silicon-based CMLIT cell. The materials of the substrate 11 are capable of withstanding the process conditions used to deposit silicon, polysilicon, silicon dioxide, and silicon nitride layers, which occurs above 400 °C. The substrate 11 can also be the product of processes like LTCC or HTCC.

[000199] While manufacturing a silicon-based CMLIT is described expressly in respect of Figures 37 A and 37B, the manufacturing process of the first through fourth embodiments as described in respect of Figures 1A to 36B may also be used to manufacture a silicon-based CMLIT so long as the substrate 11 used is made of a material that can withstand the temperatures required for silicon-based CMUTs to be manufactured (i.e. , above 400 °C) and solvents compatible with the selected substrate 11 and materials deposited thereon are used, as described above. PolyCMUTs may analogously be fabricated on a ceramic substrate.

Operation

[000200] Figures 38A and 38B respectively depict the front side 211 and back side 212 of a wafer substrate 210 fabricated in a PCB manufacturing facility. The wafer substrate front side 211 has several hundred exposed vias 21 and annular rings 22, which are too small to be individually identified in Figure 38A. The position of these vias 21 and annular rings 22 matches the position of polyCMUT arrays 204 that will be fabricated on this wafer substrate front side 211. The wafer substrate back side 212 has several hundred contact pads that are respectively electrically connected to the vias 21 on the wafer substrate front side 211 . These electrical contact pads allow the soldering of electrical contact assemblies 230 (not shown in Figure 38A or 38B) such as headers or receptacles used in the PCB industry to permit interaction with external electronic equipment such as ultrasound pulsers and amplifiers.

[000201] Referring now to Figure 39A and Figure 39B, there are respectively shown top isometric and top plan views of a 3D visualization of a polyCMUT array 204 in the form of a polyCMUT linear array 202 fabricated on a substrate 11. The polyCMUT linear array 202 is one of the multiple arrays 202 manufactured from the wafer substrate 210 of Figures 38A and 38B. The polyCMUT linear array 202 is comprised of 128 polyCMUT elements 201 stacked on each other along the length of the array 202, with each of the polyCMUT elements comprising around 300 polyCMUT cells (not individually shown). The polyCMUT elements are respectively electrically connected to independent vias 21 (not individually shown) on the substrate 11 that extend through to the substrate’s 11 bottom side 13. An electrical contact assembly 230 is mounted on the bottom side 13 of the substrate 11 and is electrically connected to the vias 21. The 128 polyCMUT elements are respectively electrically coupled to 128 of the vias 21 . The polyCMUT linear array 202 is fabricated on top of a polished substrate 30 according to the first embodiment described above and depicted in accordance with Figures 1 A to 9B.

[000202] Referring now to Figure 40A and Figure 40B, there are respectively shown isometric and bottom views of a 3D visualization of the bottom side 13 of the polyCMUT linear array 202 of Figures 39A and 39B. The polyCMUT linear array 202, being on the top side of the substrate 11 , is not shown. The electrical contact assembly 230 has several dozen independent electrical contact assembly connections 231. Each of these electrical contact assembly connections 231 connects to a via 21 and accordingly is also electrically connected to the second conductive material 115 of their corresponding polyCMUT elements 201 (not shown).

[000203] Referring now to Figure 41 , there is shown a cross-sectional view of the polyCMUT linear array 202 of Figures 39A and 39B. On the top side 12 is a polyCMUT element 201 fabricated on top of a polished substrate 30 through which extend vias 21 leading to annular rings 22 located on the bottom side 13. The electrical contact assembly 230, which contains electrical contact assembly connections 231 , is adhered to the substrate conductive contact area 26. Each individual electrical contact assembly connection 231 is connected to an individual via 21 through the substrate conductive contact area 26 that is patterned on the bottom side 13 of the substrate 11 . This substrate conductive contact area 26 is typically patterned by the fabrication facility (e.g., a PCB factory)

[000204] Referring now to Figure 42A and Figure 42B, a top isometric view and a bottom isometric view of a polyCMUT array 204 are respectively shown. A polyCMUT matrix array 203 comprising hundreds of polyCMUT elements 201 arranged in several dozen rows and columns is fabricated on top of a polished substrate 30. On the bottom side 13, there exist several hundred substrate conductive contact areas 26 isolated electrically one another. These substrate conductive contact areas 26 respectively have direct access from the bottom side 13 to individual polyCMUT elements 201 on the top side 12 through vias 21 (not shown) extending through the polished substrate 30. The polished substrate 30 can comprise one or more layers of substrate conductive material 23 that allow the proper routing and distribution of the substrate conductive contact areas 26. For instance, printed circuit boards may have two, four, six, or more layers interconnected by inner vias.

[000205] Referring now to Figure 43A and Figure 43B, the top view and the detailed view of area A of the top view of the polyCMUT array 204 of Figures 42A and 42B are respectively illustrated. A polyCMUT matrix array 203 comprising hundreds of polyCMUT elements 201 in several dozen rows and columns along the X and Y axes is fabricated on top of a polished substrate 30. The polyCMUT matrix array 203 has independent connections for the top and bottom electrodes of the polyCMUT cells in some embodiments (not shown). The polyCMUT matrix array 203 has independent connections for the top electrode and a common electrical connection for the bottom electrode (not shown) in some embodiments.

[000206] Referring now to Figure 44A and Figure 44B, the bottom view and a detailed view of area A of the top view of the polyCMUT array 204 of Figures 42A and 42B are shown, respectively. There exists an array of substrate conductive contact areas 26 isolated electrically one from another that respectively have direct electrical access to individual polyCMUT elements 201 on the top side 12 through vias 21 (not shown) extending through the polished substrate 30. The polished substrate 30 can comprise one or more layers of substrate conductive material 23 that allow the proper routing and distribution of the substrate conductive contact areas 26. For instance, printed circuit boards may have two, four, six or more layers interconnected by inner vias.

[000207] Referring now to Figure 45A and Figure 45B, a bottom view and a detailed view of area A of a polyCMUT array 204 are shown, respectively. An electrical contact assembly 230 (shown as a dashed rectangle) is mounted on the bottom side 13 of the polyCMUT array 204. The detailed view shows the substrate conductive contact area 26 that has a split section, forming substrate conductive contact tracks 27 that then lead to the annular rings 22. An electronic component 241 (e.g., a surface mounted device such as an inductor) can be soldered or adhered between the substrate conductive contact tracks 27 to act as an electrical impedance matching circuit to counteract the capacitive reactance typical of CMUTs and polyCMUTs. The substrate conductive contact area 26 can be split into two or more substrate conductive contact tracks 27 (not shown) to permit mounting of two or more electronic components 241 ; for instance, an array comprising a resistor and a capacitor may be mounted to respective substrate conductive contact tracks 27 to create a “bias-tee” circuit to add DC and AC voltages.

[000208] Referring now to Figures 46A, 46B, 46C and 46D, the top view, the cross- sectional view taken along line A-A’ of Figure 46A, the rear view, and the detailed view of area B of Figure 46B of the polyCMUT array 204 of Figure 45A are respectively shown. A polyCMUT linear array 202 comprised of polyCMUT elements 201 is built on a polished substrate 30. The substrate 11 is comprised of two or more substrate sublayers 16 arranged in a stack. Internal vias 21 and internal substrate conductive materials 23 are present between the substrate sublayers 16, although not depicted in Figures 46A-46D. There are buried regions 250 in the substrate 11 that can contain a plurality of embedded electronic components 241 , such as inductors, resistors, capacitors, microprocessors, or a circuit formed by these embedded electronic components 241. These embedded electronic components 241 can be electronically connected to individual polyCMUT elements 201 or a plurality of polyCMUT elements 201. This integration helps to reduce the overall footprint of a polyCMUT array 204 interacting with embedded electronic components 241. These embedded electronic components 241 can be directly integrated at the time of manufacture, or can be added after the substrate 11 is finalized by etching some areas on the bottom side 13 thereof and then filling those areas with a material having similar mechanical and chemical properties as the substrate 11 , such FR4 resin.

[000209] Referring now to Figure 47, an exploded view of a transducer assembly 250 is shown. It comprises an electrical contact assembly 230. The electrical contact assembly 230 comprises a plurality of electrical contact assembly connections 231 , and is attached (e.g., adhered or soldered) to the polyCMUT array 204. This polyCMUT array 204 can be either a polyCMUT linear array 202 or a polyCMUT matrix array 203 (not shown). An acoustic lens 240 is also attached (e.g., adhered or casted) to the top surface of the polyCMUT array 204. The purpose of this acoustic lens 240 is to generate a concentrated ultrasound beam. In some embodiments, this acoustic lens 240 can be casted directly on top of the polyCMUT array 204 using a mold (not shown) or, in other embodiments, can be casted on a separate mold and then glued in place using an adhesive compatible with the material of the acoustic lens 240 and the polyCMUT array 204.

[000210] Referring now to Figures 48A, 48B, and 48C, three cross-sectional views of a polyCMUT linear array 202 with different thicknesses (T4, T5, and T6) of the substrate 11 are illustrated, and the individual polyCMUT elements 201 can be seen on the top sides thereof. Thicker substrates (T4) lead to larger radius of curvature (R4) when the polyCMUT linear arrays 202 are bent around the X axis (not shown, axis coming out of the page) such that T4 > T5 > T6 and R4 > R5 > R6. In some embodiments, some substrates 11 having vias 21 (not shown) can be fabricated in thin substrates (typically 0.4 mm thick) that lead to a semi-rigid/bendable polyCMUT linear array 202.

Examples

[000211] Referring now to Figure 49A, a picture of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is illustrated. The wafer substrate front side 211 has several hundred exposed vias 21 and annular rings 22 (too small to be individually identified in Figure 49A). The positions of these vias 21 and annular rings 22 match the position of polyCMUTs arrays 204 to be fabricated on this wafer substrate front side 211 . The detailed view of area A is shown in Figure 51 .

[000212] Referring now to Figure 49B, a picture of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is shown. The wafer substrate back side 212 has several hundred electrical contact pads that have electrical individual access to the vias 21 on the wafer substrate front side 211. These electrical contact pads allow the soldering of electrical contact assemblies 230 (such as headers or receptacles used in PCB industry) for the interaction with external electronic equipment such as ultrasound pulsers and amplifiers. The detailed view of area B is shown in Figure 50A.

[000213] Referring now to Figure 50A, the detailed view of area B that appears in Figure 49B is shown. It corresponds to the microscopic view of the wafer substrate back side 212.

[000214] Referring now to Figure 50B, the detailed view of area C that appears in Figure 50A is illustrated. It corresponds to the microscopic view of the wafer substrate back side 212. The annular rings 22 are electrically connected to the substrate conductive contact areas 26 through a plurality of substrate conductive tracks 27 patterned using the same substrate conductive material 23.

[000215] Referring now to Figure 51 , the detailed view of area A that appears in Figure 49A is shown. It corresponds to the microscopic view of the wafer substrate front side 211 . A polished substrate 30 was achieved by using a mechanical grinding and polishing system, alongside with polishing chemicals and abrasive agents. Some polished vias 31 are also shown; these polished vias will be used to connect to the top electrodes in individual polyCMUT elements 201 that will be fabricated on top (not shown). The polishing system planarized the wafer substrate front side 211 uniformly until a surface roughness of a few nm were achieved. [000216] Referring now to Figure 52A, the surface roughness measurement of the wafer substrate front side 211 along a distance L (shown in Figure 51 ) before a polishing stage is shown. The average surface roughness is 2.092 urn. This measurement was acquired using a DektakXT™ needle profilometer.

[000217] Referring now to Figure 52B, the surface roughness measurement of the wafer substrate front side 211 along a distance L (shown in Figure 51 ) after a polishing stage is illustrated. The average surface roughness is 52.805 nm. This measurement was acquired using a DektakXT™ needle profilometer.

[000218] Referring now to Figure 53A, a picture of a wafer substrate 210 with several polyCMUT arrays 204 fabricated on top after the wafer substrate 210 was polished in a grinding/lapping machine is shown. There are seven identical polyCMUT linear arrays 202 located in the center, plus three additional polyCMUT linear arrays 202 located on the sides. There is also a small polyCMUT matrix array 203 located on the northwest corner. This wafer substrate 210 will be later diced in a dicing saw to individually separate the polyCMUT arrays 204.

[000219] Referring now to Figure 53B, a picture of a polyCMUT group of arrays 205 is illustrated. The polyCMUT arrays 204 were separated using a dicing saw. Just a few of the polyCMUT linear arrays 202 are shown in this picture.

[000220] Referring now to Figure 54A, a picture of a polyCMUT linear array 202 fabricated on a substrate 11 (also shown in Figure 53B) is shown. The polyCMUT linear array 202 is comprised of 128 polyCMUT elements 201 electrically connected to independent vias 21 (too small to be individually signaled in Figure 54A) on the substrate 11 . An electrical contact assembly 230 is mounted on the bottom side 13 of the substrate 11 . The polyCMUT linear array 202 was fabricated on top of a polished substrate 30 according to the first embodiment described above.

[000221] Referring now to Figure 54B, a picture of a polyCMUT linear array 202 mounted on an electrical test circuit board 233 is shown. The electrical contact assembly 230 mounted on the back side of the polyCMUT linear array 202 interfaces with an electrical contact mating connection 232 that is integrated into the electrical test circuit board 233. This electrical test circuit board 233 is used to send and receive electrical signals to and from the polyCMUT linear array 202.

[000222] The polyCMUT linear array 202 shown in Figure 54B was partially immersed (positioned facing down) in an acoustic evaluation tank (not shown) containing de-ionized water (DI water). A calibrated hydrophone manufactured by Onda Corporation of Sunnyvale, CA, USA was immersed in this acoustic evaluation tank and positioned 20 mm away from the surface of the polyCMUT linear array 202 to measure the acoustic signal generated by an individual polyCMUT element 201. The recorder signal in time is shown in the graph of Figure 55A. An acoustic signal of 73 kPa was recorded by the hydrophone.

[000223] Referring now to Figure 55B, a Fast-Fourier transform (FFT) signal corresponding to the time-domain signal shown in Figure 55A is shown. A center frequency of 7.4 MHz and a fractional bandwidth of 83% is shown when a 30 V AC voltage combined with a 30 V DC voltage is applied to the polyCMUT element 201. This demonstrates that the fabrication and operation of polyCMUT arrays 204 is possible with pre-fabricated substrates with vias and electrical connections at the back.

[000224] Referring now to Figure 56A, the computer design of a wafer substrate 210 to be fabricated in a printed circuit board manufacturing facility is illustrated. The polished substrate conductive material 33 and polished conductive areas 35 for the top electrodes are shown in the inset. The polished substrate conductive material 33 comprises more than 95% of the total area of the wafer substrate 210.

[000225] Referring now to Figure 56B, a picture of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is shown. The wafer substrate back side 212 has several hundred electrical contact pads that are respectively electrically coupled to the vias 21 on the wafer substrate front side 211. These electrical contact pads allow the soldering of electrical contact assemblies 230 (such as headers or receptacles used in PCB industry) to permit interaction with external electronic equipment such as ultrasound pulsers and amplifiers.

[000226] Referring now to Figure 57 A, a picture of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is illustrated. The substrate conductive material 23 (not shown) is protected by a planarization layer 40 fabricated using standard solder mask in a PCB fabrication facility.

[000227] Referring now to Figure 57B, the picture of a wafer substrate 210 from Figure 57A after polishing is shown. A chemical-mechanical polishing (CMP) machine was used to simultaneously polish the substrate conductive area 24 for the bottom electrodes, the substrate conductive area 25 for the top electrodes, and the planarization layer 40. The result is a wafer substrate 210 with a polished conductive area that acts as the bottom electrodes 34 with a mirror-like finishing, a similarly polished conductive area 35 for top electrodes, and a polished planarization layer 50.

[000228] Referring now to Figure 58A, a picture taken using a microscope of a region of the substrate from Figure 57B is shown. A mirror-like finishing of the polished conductive area that acts as the bottom electrodes 34 reflects some of the light from the microscope lamp.

[000229] Referring now to Figure 58B, a zoomed-in view of Figure 58A is shown. The polished conductive area that acts as the bottom electrodes 34, the polished conductive areas 35 for the top electrodes, and the polished planarization layer 50 are shown.

[000230] Referring now to Figure 59A, a picture of a needle profilometer with the substrate from Figure 57B is shown. The profilometer is used to measure the surface roughness of the polished conductive area that acts as the bottom electrodes 34.

[000231] Referring now to Figure 59B, the profilometer measurement along the longitudinal axis (refer to line Y-Y’ from Figure 57B) of the substrate from Figure 59A is shown. The 80 mm-long measurement shows the curvature or “bow” of the substrate alongside with some surface roughness parameters. [000232] Referring now to Figure 59C, the profilometer measurement along the transverse axis (refer to line X-X’ from Figure 58B) of the substrate from Figure 59A is shown. The 1.6 mm-long measurement shows the surface profile of the polished conductive area for top electrode 35 and the polished planarization layer 50.

[000233] Referring now to Figure 60A, the profilometer measurement along the X and Y axes of a standard 100mm prime-grade silicon wafer with an oxide layer is shown. This was performed to measure the curvature or “bow” of a typical silicon wafer used in microfabrication. The wafer bow is between 20 urn and 30 urn.

[000234] Referring now to Figure 60B, the measurement data along the X and Y axes of the substrate from Figure 59A is shown. The wafer bow is between 30 urn and 40 urn, which is very comparable to the bow of a standard silicon wafer. This means that the wafer substrate 210 is compatible to be processed in standard microfabrication equipment.

[000235] Referring now to Figure 61 A, the profilometer measurement along the center region of a standard 100mm prime-grade silicon wafer with an oxide layer is shown. This was performed to measure the surface roughness of a typical silicon wafer used in microfabrication. The wafer roughness is between 20 nm to 40 nm.

[000236] Referring now to Figure 61 B, the profilometer measurement along the center region of the substrate from Figure 59A is shown. The surface roughness is between 0 nm to 30 nm, very comparable to surface roughness of a standard silicon wafer. This means that the wafer substrate 210 is suitable for processing using standard microfabrication equipment and can be used for the direct fabrication of polyCMUT arrays 205.

[000237] Referring now to Figure 62A, the profilometer measurement along the polished planarization layer 50 of the substrate from Figure 59A is shown. The surface roughness is between -40 nm to 20 nm. This means that the first polymer layer 110 and the top electrode interconnect 117 can be patterned directly, as discussed in respect of Figure 25B. [000238] Referring now to Figure 62B, the profilometer measurement 100um along the region of the substrate from Figure 59A is shown. The surface roughness is between -5 nm to 5 nm.

[000239] Referring now to Figure 63, contrasted with certain ringing effects for CMUTs fabricated on silicon substrates [2] due to unwanted acoustic reflections happening in the silicon substrate that appear as notches in the frequency response, for the fabrication methodologies of the present non-silicon embodiments any ringing effects are located outside of the frequency range of interest. For example, the acoustic signal shown in Figure 55B has a center frequency of 7.4 MHz; the ringing effects in this substrate would appear around 1 .68 MHz for a substrate with a thickness of 1 mm. This frequency lies outside of the -6 dB lower frequency (around 4.0 MHz).

Advantages

[000240] Poly-CMUTs made according to at least some of the embodiments here are advantageous over traditional silicon-based CMUTs. For example, the total manufacturing cost of poly-CMUTs can in many instances be well below US$100. Minimal and inexpensive manufacturing equipment can be used for poly-CMUTs (e.g., mask aligner, metal evaporator, critical point drier). This is an advantage over silicon- based CMUTs, where expensive and cumbersome equipment is needed. The poly- CMUT arrays of at least some embodiments also possess flexibility as shown in Figures 48A, 48B, and 48C, which show bendability in either one (x) or two (x, y) dimensions. This is also illustrated in Figures 65A, 65B, 65C, 66A, 66B, and 66C. Polymer-based CMUTs can be manufactured on flexible substrates for wearable applications; as discussed above, PCBs may be flexible or rigid. This cannot be done with silicon-based CMUTs, including the silicon-based CMUT embodiment of Figures 37A and 37B, since they need rigid substrates. Similarly, flexible substrates cannot be used when fabricating CMUTs using ceramic piezoelectric materials.

[000241] Another advantage of the fabrication approach described in respect of the embodiments herein is that a multi-layer fabrication approach allows the electrical shielding of signal cables. For example, individual routing from CMUT elements can be protected between two ground planes to minimize electromagnetic interference (EMI).

[000242] The epoxy resins used in the fabrication of PCBs such as FR4 have a low X-ray mass absorption coefficient. Therefore, the substrate can be considered X-ray transparent.

[000243] The application approach described in any of the embodiments is also compatible with wafer-bonding fabrication techniques such as those described in US patent nos. 10,509,013, 10,564,132, and 10,598,632. Also, the fabrication techniques of the various embodiments herein are also compatible with more traditional chipbonding using solder bumps.

[000244] Referring now to Figure 64A and 64B, the cross-sectional front view and the cross-sectional side view respectively of a probe assembly 251 is shown. A polyCMUT array 204 with an acoustic lens 240 and an electrical contact assembly 230 is mounted on an existing probe case 252 containing an electrical contact mating connection 232 that connects to an electrical interface board 234 containing a plurality of electronic components 241 (e.g., capacitors, inductors, resistors, etc.). An advantage of the fabrication methodology described in any of the embodiments herein is that that the assembly or repair of ultrasound probes is greatly simplified. The fabrication methodology avoids the wirebonding, encapsulation, and lens casting procedures of traditional piezoelectric and silicon-based transducers.

[000245] Referring now to Figure 65A, 65B, and 65C, a probe assembly 251 comprised of a hermetically-sealed probe case 252 where a polyCMUT array 204 is mounted is shown. The probe case 252 has a single passage 260 leading to an inner chamber 261. This inner chamber 261 can be filled with gas or a liquid at different pressures (P1 , P2, or P3). The polyCMUT array is thin enough to be deflected by the pressure in the inner chamber 261 . A pressure lower than the atmospheric pressure as shown in Figures 65B and 65C causes the polyCMUT array 204 to deflect inwards towards the probe case 252. A pressure equal to atmospheric pressure results in no deflection, as shown in Figure 65A. A pressure higher than atmospheric pressure (not shown) will cause the polyCMUT array 204 to deflect outwards away from the probe case. Many or all of the polyCMUT elements in the polyCMUT array 204 may operate simultaneously to generate individual ultrasound waves 270. Depending on the deflection of the polyCMUT array 204, an unfocused ultrasound beam 271 or a focused ultrasound beam 272 can be obtained with a variable focal point 273. In some embodiments, this may be beneficial for ultrasound probes dedicated to therapeutic applications, in which a physically focused ultrasound beam 272 is desired over an electronically-focused ultrasound beam to deliver relatively high acoustic energy for an accelerated tissue healing.

[000246] Referring now to Figures 66A, 66B, and 66C, a probe assembly 251 comprised of a probe case 252 in which a polyCMUT array 204 is assembled to become an ultrasound probe is shown. The probe case 252 has a deflection mechanism 262 that is attached to the back side of the polyCMUT array 204. This deflection mechanism causes a vertical displacement 263 (D1 , D2, and D3) that induces a deflection of the polyCMUT array 204. The polyCMUT array 204 is thin enough to be deflected by the deflection mechanism 262. Many or all of the polyCMUT elements 201 in the polyCMUT array 204 can operate simultaneously to generate individual ultrasound waves 270. Depending on the deflection of the polyCMUT array 204, an unfocused ultrasound beam 271 or a focused ultrasound beam 272 can be obtained with a variable focal point 273. In some embodiments, this may be beneficial for ultrasound probes dedicated for therapeutic applications, where a physically focused ultrasound beam 272 is desired over an electronically-focused ultrasound beam to deliver relatively high acoustic energy for accelerated tissue healing.

[000247] Referring now to Figure 67, a polyCMUT linear array 202 comprised of polyCMUT elements 201 (not identified individually) is built on a polished substrate 30. The polished substrate 30 is comprised of two or more substrate sublayers 16 (not identified individually) stacked on each other. Internal vias 21 (not shown) and internal substrate conductive materials 23 (not shown) are between the substrate sublayers 16. One or more a planar inductors 242 are fabricated on the surface of either of the substrate layers 16. These planar inductors 242 are capable of generating and receiving a wireless signals, such as for power, similar to a wireless charger, or for data communication. A potential application of the array 202 of Figure 67 is a fully wireless polyCMUT array 204.

[000248] In this disclosure the recitation of numerical ranges by endpoints includes all numbers subsumed within that range including all whole numbers, all integers and all fractional intermediates (e.g., 1 to 5 includes 1 , 1.5, 2, 2.75, 3, 3.80, 4, and 5 etc.).

[000249] A reference to a value being “about” or “approximately” a quantity means that value is within +/- 10% of that quantity unless the context indicates otherwise.

[000250] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Accordingly, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise (e.g., a reference in the claims to “a via” or “the via” does not exclude embodiments in which multiple vias are used; and references to fabricating “a bottom electrode” and “a top electrode” include references where an array of bottom electrodes and top electrodes are being fabricated). It will be further understood that the terms “comprises” and “comprising”, when used in this specification, specify the presence of one or more stated features, integers, steps, operations, elements, and components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and groups. Directional terms such as “top”, “bottom”, “upwards”, “downwards”, “vertically”, and “laterally” are used in the following description for the purpose of providing relative reference only, and are not intended to suggest any limitations on how any article is to be positioned during use, or to be mounted in an assembly or relative to an environment. Additionally, the term “connect” and variants of it such as “connected”, “connects”, and “connecting” as used in this description are intended to include indirect and direct connections unless otherwise indicated. For example, if a first device is connected to a second device, that coupling may be through a direct connection or through an indirect connection via other devices and connections. Similarly, if the first device is communicatively connected to the second device, communication may be through a direct connection or through an indirect connection via other devices and connections.

[000251] Phrases such as “at least one of A, B, and C”, “at least one of A, B, or C”, “one or more of A, B, and C”, and “A, B, and/or C” are intended to include both a single item from the enumerated list of items (i.e., only A, only B, or only C) and multiple items from the list (i.e., A and B, B and C, A and C, and A, B, and C). Accordingly, the phrases “at least one of”, “one or more of”, and similar phrases when used in conjunction with a list are not meant to require that each item of the list be present, although each item of the list may be present.

[000252] It is contemplated that any part of any aspect or embodiment discussed in this specification can be implemented or combined with any part of any other aspect or embodiment discussed in this specification, so long as such those parts are not mutually exclusive with each other.

[000253] The scope of the claims should not be limited by the embodiments set forth in the above examples, but should be given the broadest interpretation consistent with the description as a whole.

[000254] It should be recognized that features and aspects of the various examples provided above can be combined into further examples that also fall within the scope of the present disclosure. In addition, the figures are not to scale and may have size and shape exaggerated for illustrative purposes.

REFERENCES

[1] 0. Oralkan et al., “Capacitive micromachined ultrasonic transducers: Next-generation arrays for acoustic imaging?,” Ultrason. Ferroelectr. Freq. Control IEEE Trans. On, vol. 49, no. 11 , pp. 1596-1610, 2002. [2] K. R. Chapagain, “Integration of Electronics and Mechanics in Next Generation

Ultrasound Transducers in Medical Imaging,” NTNU, 2014. Accessed: Dec. 21 , 2021. [Online], Available: https://ntnuopen.ntnu.nO/ntnu-xmlui/handle/11250/2370933