Title:
CELL MANAGEMENT CIRCUIT, POWER STORAGE DEVICE, AND ELECTRICAL APPARATUS
Document Type and Number:
WIPO Patent Application WO/2020/008297
Kind Code:
A1
Abstract:
To provide a cell management circuit having a novel structure, and a power storage device provided with the cell circuit. This power storage device has a plurality of cells connected in series, and a cell management circuit. The cell management circuit has a voltage monitor circuit having a function for acquiring the voltage value between a pair of electrodes in any one of the cells. The voltage monitor circuit has a multiplexer and a buffer circuit for outputting a signal for controlling the multiplexer. The multiplexer and the buffer circuit are constituted from n-channel-type transistors. The n-channel-type transistors are transistors in which a channel formation region has an oxide semiconductor. The multiplexer has a function for holding the output voltage of a cell by placing a transistor in the OFF state.
Inventors:
TAKAHASHI KEI (JP)
KUSUNOKI KOJI (JP)
TOYOTAKA KOUHEI (JP)
WATANABE KAZUNORI (JP)
KUSUNOKI KOJI (JP)
TOYOTAKA KOUHEI (JP)
WATANABE KAZUNORI (JP)
Application Number:
PCT/IB2019/055319
Publication Date:
January 09, 2020
Filing Date:
June 25, 2019
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
G01R19/165; G01R31/388; H01L29/786; H02J7/02; H03K17/00
Domestic Patent References:
| WO2018051442A1 | 2018-03-22 |
Foreign References:
| JP2007101317A | 2007-04-19 | |||
| JP2014143185A | 2014-08-07 | |||
| JP2015023698A | 2015-02-02 | |||
| JP2007232417A | 2007-09-13 | |||
| JP2013534618A | 2013-09-05 | |||
| US7221192B1 | 2007-05-22 |
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