CONTROL

CLAIM OF PRIORITY

[0001] This patent application claims the benefit of priority to U.S.

Application Serial No. 16/217,878, filed December 12, 2018, which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

[0002] Embodiments described herein pertain to supply power in integrated circuits. Some embodiments relate to charge pump circuitry.

BACKGROUND

[0003] Charge pumps are commonly used electronic devices to generate a higher supply voltage from a lower supply voltage. Many conventional charge pumps have techniques to improve charge pump efficiency relative to output current by reducing the operating frequency of the charge pump (so called clock- skipping technique). Such conventional techniques can deteriorate the quality of the output voltage of the charge pump in terms of output voltage ripple and noise performance. Therefore, such conventional charge pumps are unfavorable for use in systems that are noise-sensitive.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 shows an apparatus including a voltage generator and a load, according to some embodiments described herein.

[0005] FIG. 2 shows an equivalent circuit of a charge pump of the voltage generator of FIG. 1, according to some embodiments described herein.

[0006] FIG. 3 shows a voltage generator, according to some

embodiments described herein.

[0007] FIG. 4 shows an apparatus in the form of an electronic system, according to some embodiments described herein. DETAILED DESCRIPTION

[0008] The techniques described herein involve a feedback mechanism built into a charge pump system. The charge pump system includes a charge pump that can be part of a voltage generator. The feedback mechanism can monitor output current of the charge pump system and generate feedback information, which can include a reference voltage. The described techniques use the reference voltage to adjust one of the supply voltages used by the charge pump. The adjustment can reduce the power losses related to the switching of the charge pump without sacrificing the quality of the output voltage in terms of noise and ripples. The adjustment improves the efficiency of the charge pump in some operating conditions of a load that uses power from the charge pump.

Other improvements and benefits of the described techniques are discussed below. The described techniques can be used in many systems where noise sensitivity is a factor.

[0009] FIG. 1 shows an apparatus 100 including a voltage generator 101 and a load 102, according to some embodiments described herein. Apparatus 100 can include or be included in an electronic device or systems. Examples of such devices or systems include computers (e.g., servers, desktops, laptops, and notebooks), tablets, cellular phones, wearable electronic things, Internet of Things (IoT), an integrated circuit chip (e.g., a processor), and other electronic devices or systems.

[0010] As shown in FIG. 1, apparatus 100 can include a node (e.g., supply power node) 103 to receive a voltage (e.g., input supply voltage) YIN and a node (e.g., regulator output node) 104 to provide a voltage (e.g., a regulated output voltage) VREG DUT. Supply power node 103 can be part of a supply power rail (e.g., VDD power rail) of apparatus 100 that can receive supply power from a battery (not shown) through a power path coupled to the battery. Such a power path may include circuitry (e.g., supply voltage regulating circuity, not shown in FIG. 1) to receive supply power from the battery and generate a voltage, which can include voltage VIN.

[0011] As shown in FIG. 1, voltage generator 101 can include a charge pump 110 that can receive voltages (e.g., supply voltages) VIN and VPH and a clock signal CLK at nodes 103, 105, and 106, respectively. Charge pump 1 10 can include stages that can operate based on timing (e.g., phases) of clock signal CLK to generate a voltage (e.g., output voltage) VOUT at node 107 based on voltages VIN and VPH.

[0012] Charge pump 1 10 can use voltage VIN for some of its components to generate voltage VOUT. Charge pump 1 10 can also use voltage VPH as supply voltage (e.g., phase voltage supply) for some other circuit components (e.g., switching circuit, not shown) of charge pump 110. Such other components can include transistors that may operate at an operating voltage (e.g., a maximum tolerance voltage) having a value less than the value of voltage VIN. Thus, in addition to voltage VIN, charge pump 110 may use voltage VPH (e.g., VPH < VIN) as a second supply for components of charge pump 1 10 that use a supply voltage having a value less than the value of voltage VIN.

[0013] As shown in FIG. 1, voltage generator 101 can include an output regulator 120 to regulate voltage VOUT and generate a noise and ripple-free voltage (e.g., charge pump regulated output voltage) VREG OUT based on voltage VOUT. Load 102 can use voltage VREGJXJT as its supply voltage or as a voltage to control components (e.g., control the gates of switching transistors in load 102).

[0014] Load 102 can include or can be part of an electronic unit which may require low noise and low ripple supply (e.g., antenna signal path in transceiver part of a modem), transmitter, a receiver, or part of other types of electronic units. Load 102 may have different operational states that may include a higher power consumption state (e.g., active state) and a lower power consumption state (e.g., an inactive state, such as a sleep state). Load 102 may consume a relatively higher current in the higher power consumption state and a relatively lower current in the lower power consumption state. Current lour at node 104 can represent current provided to load 102. Thus, the value of current lour can be relatively high when load 102 is in the higher power consumption state and relatively low when load 102 is in the lower power consumption state.

[0015] Voltage generator 101 can include a phase supply voltage controller 130 that can operate to receive a voltage (e.g., a reference voltage) VREF. Phase supply voltage controller 130 can control (e.g., adjust) the value of voltage VPH based on the value of voltage VREF.

[0016] Voltage generator 101 can include a monitor circuit 140, which can operate to monitor current IOUT and generate voltage VREF. The value of voltage VREF is based on the value of current Ioux. For example, the value of voltage VREF can be proportional to the value of current IOUT, such that the higher the value of current IOUT the higher the value of voltage VREF, and the lower the value of current IOUT the lower the value of voltage VREF.

[0017] Monitor circuit 140 can monitor current IOUT and generate feedback information, which can include voltage VREF. AS described above, phase supply voltage controller 130 can use voltage VREF to adjust the value of voltage VPH.

[0018] As mentioned above and as described in more detail below, the techniques described herein involve mechanisms to improve the efficiency of a charge pump (e.g., charge pump 1 10) based on operating conditions of load 102. As mentioned above, the value of current IOUT can indicate the operating conditions of load 102. To optimize the efficiency of a charge pump 110 based on current IOUT, the following description describes the efficiency of a charge pump (which can be a model for charge pump 1 10) based on current IOUT provided to a load and based on other parameters (e.g., circuit elements) associated with the charge pump.

[0019] FIG. 2 shows an equivalent circuit of charge pump 110 of the voltage generator of FIG. 1 , according to some embodiments described herein. As shown in FIG. 2, the equivalent circuit of charge pump 110 can be represented by a voltage source VCPour connected in series with an output resistance Rs. Capacitor CLOAD and resistor RLQAD represent a load (e.g., load 102 of FIG. 1) coupled to charge pump 1 10. Current IOUT and voltage Voux represent current and voltage, respectively, provided to the load 102 from charge pump 110.

[0020] In FIG 2, voltage VCPour represents the output voltage of charge pump 110. For simplicity, the following discussion assumes that voltage VCPour is an output voltage of a basic N- stage Dickson charge pump architecture where N = 2. However, the following discussion can be applicable to Dickson charge pump architecture having more than two stages (e.g., N > 2). For a 2-stage (N = 2) Dickson charge pump architecture, voltage VCPour can be expressed as follows.

[0021] VCPOUT = VIN + 2 * [(C / (C+Cs)) * V _PH -Vo] - VD (1)

[0022] In equation (1), symbol“*” represents multiplication and symbol represents division,“C” represents the charge pump stage capacitance,“Cs” represents a stray capacitance related to a single charge pump stage, and“V _D ” represents a threshold voltage of a diode. Voltages V _® and V _PH represent input voltage (e.g., supply voltage (e.g., VDD)) and phase supply voltage,

respectively, of charge pump 1 10, as described above with reference to FIG. 1.

[0023] Output resistance Rs of FIG. 2 can be expressed according to

Dickson charge pump architecture as follows.

[0024] Rs = 2 / [(C + Cs) * fs] (2)

[0025] In equation (2),“fs” is the frequency of clock signal CLK supplying the charge pump phases.

[0026] In FIG. 2, a ripple voltage VRIPPLE can occur in voltage VQUT and can be described in a simplified way as follows.

[0027] VRIPPLE = VOUT / (fs * RLOAD * CLOAD) (3)

[0028] The effective output voltage (e.g., VQ _UT ) of charge pump 1 10 can be expressed as follows.

[0029] VOUT = VCPOUT - (Rs * IOUT) (4)

[0030] Based on equation (3), ripple voltage VRIPPLE depends inverse proportionally on frequency fs of clock signal CLK used by charge pump 110 and proportionally to voltage VOUT of charge pump 110.

[0031] The effi ciency (h) of charge pump 110 can be defined as follows.

[0032] h = (VO _UT * IO _UT ) / (VO _UT * IO _UT ) + P__res + P__dyn (5)

[0033] In equation (5), VOUT * IOUT represents the output power of charge pump 1 10, and“P res” and“P_dyn” represent resistive loss and dynamic loss (e.g., switching loss), respectively, and can be expressed as follows.

[0034] P res = Rs * IOUT ² (6)

[0035] P dyn = k * N * fs * Cs * V _PH ² (7)

[0036] In equation (7),“k” is a coeffici ent of proportionality. [0037] Combining equations (6) and (7) with equation (5) yields the generic representation of the charge pump efficiency as follows.

[0038] h = (VOUT * TOUT) / (VQUT * TOUT) + (Rs * loux ³ ) + (k * N * fs * Cs * VPH ² )

(8)

[0039] In some operating conditions, the load (e.g., load 102) may consume a relatively low power (e.g., low or medium current). Without the techniques described herein, the efficiency of charge pump 110 may be relatively low in such operation conditions due to low power delivered to the load, small resistive power losses, and dominant switching power loses. The techniques described herein help improve the efficiency of charge pump 110 in such operation conditions. As described in more detail below, the described techniques include a mechanism that can adjust and optimize a supply voltage (e.g., voltage VPH) provided to charge pump 1 10 based on an output current (e.g., IOUT). Further, optimizing the supply voltage (e.g., voltage VPH) provided to charge pump 110 can also lead to optimizing of the power delivered to the load.

[0040] The techniques described herein include monitoring a load current (e.g., IOUT) and generating feedback information to adjust the output voltage (e.g., VOUT) of the charge pump to improve charge pump efficiency. As a result, the output voltage can be relatively stable and constant (e.g., ripple at the output voltage is minimized), independent of charge pump loading conditions (e.g., see equation (4)). This can improve charge pump efficiency such as by reducing the dynamic losses (e.g., switching losses) when the charge pump operates with a relatively low load current.

[0041] Referring to FIG. 1, charge pump 110 can generate voltage VOUT based on equations 1 and 4. Output regulator 120 can operate to regulate voltage VOUT to provide precise and ripple-free (or reduced ripple) voltage (e.g.,

VREG OUT). The operation of output regulator 120 is beneficial from the noise and ripple performance point of view, as mentioned earlier. Current IOUT is monitored (e g., sensed) by monitor circuit 140 and generate feedback monitor information (e.g., monitored information) that can include voltage VREF. Phase supply voltage controller 130 uses voltage VREF to adjust the value of voltage VPH. Based on equation (4) VOUT = VCPOUT - (Rs * IOUT), it can be seen that the lower the value of current IOUT the higher the value of voltage VOUT. Thus, the value of voltage VOUT can reach the value of voltage VCPOUT if the value of current IOUT is zero (e.g., at no load current or at a negligible amount of load current). The excess of voltage VOUT coming from a small value of Rs* IOUT can be compensated by lowering the value of voltage VCPOUT by means of a reduction in the value of voltage VPH. With this reduction technique, the performance of voltage generator 101 can remain unchanged. However, the dynamic losses (e.g., switching losses) as described by equation (7) are reduced and overall charge pump efficiency increases. When the value of current IOUT increases, the value of voltage VREF increases. This in turn increases the value of voltage VPH in order to compensate for the voltage drop on resistor Rs, as described in equation (4). Thus, although the efficiency of charge pump 110 is improved in some operating conditions (e.g., at a relatively lower value of current IOUT), efficiency improvement of charge pump 1 10 in some other operating conditions can be relatively less (e.g., at a relatively higher value of current IOUT).

[0042] FIG. 3 shows an apparatus 300 including voltage generator 301 and a load 302, according to some embodiments described herein. Load 302 can include load 102 of FIG. 2 and can be represented by capacitor CLOAD and resistor RLOAD as shown in FIG. 3.

[0043] As shown in FIG. 3, voltage generator 301 can include a charge pump 310, an output regulator 320, a phase supply voltage controller 330, and a monitor circuit that includes a combination of a current sensor 341 and a current to voltage converter 342.

[0044] Charge pump 310 can include diodes Dl, D2, and D3 coupled in series between nodes 303 and 307, capacitors Cl and C2, a switching circuit (e.g., phase driver circuit) 31 1 that includes transistors P 1 , P2, N 1 , and N2, and an inverter INV. Nodes 303 and 307 can be input and output nodes,

respectively, of charge pump 310. Node 303 can receive voltage VIN. Node 307 can provide voltage VOUT. Switching circuit 311 can operate (e.g., turn on and turn off transistors PI, P2, Nl, and N2) based on timing (e.g., the phases) of clock signal CLK. Charge pump 310 can include a node 305 to receive voltage VPH, which can be used as supply voltage for switching circuit 311. The value of voltage VPH can be less than the value of voltage VIN (e.g., VPH < VIN).

[0045] Output regulator 320 can include an operational amplifier 321, a transistor N, and resistors R1 and R2. Output regulator 320 can generate voltage VREG OUT at a node (e.g., regulator output node) 304 based on voltage VOUT and a voltage VBG (e.g., a bandgap voltage). Output regulator 320 can also provide current lour at node 304.

[0046] Phase supply voltage controller 330 can include a transistor P5 and an operational amplifier 331 that forms a voltage follower output circuit to generate voltage VPH based on voltage VREF (e.g., VPH = VREF voltage).

[0047] Current sensor 341 can include transistors P3 and P4. Voltage converter 342 can include a transistor P4, a current source 343, a resistor RREF, and a diode D.

[0048] In operation, switchi ng circui t 31 1 can be part of two charge pump stages of charge pump 310. One stage of charge pump 310 can include transistors PI and Nl. Another stage of charge pump 310 can include transistors P2 and N2.

[0049] As shown in FIG. 3, transistors PI and Nl have gates to receive clock signal CLK. Transistors PI and N 1 can form a driver (e.g., phase driver) that can operate (e.g., alternately turn on and turn off) to couple a plate (e.g., bottom plate) of capacitor Cl to either ground or node 305 based on the phases (e.g., signal levels) of clock signal CLK.

[0050] Transistors P2 and 2 have gates to receive clock signal (through inverter INV). Transistors P2 and N2 can form a driver (e.g., phase driver) that can operate (e.g., alternately turn on and turn off) to couple a plate (e.g., bottom plate) of capacitor C2 to either ground or node 305 based on the phases (e.g., signal levels) of clock signal CLK.

[0051] As show in FIG. 3, capacitor Cl can include a bottom plate directly coupled to an output node (node between transistors P I and Nl) of a driver that includes transistors PI and NL Capacitor C2 can include a bottom plate directly coupled to an output node (node between transistors P2 and N2) of a driver that includes transistors P2 and N2. In response to one phase (a“low” level) of clock signal CLK during operation of charge pump 310, the bottom plate of capacitor Cl can be coupled to node 305 (to voltage VPH), and the bottom plate of capacitor C2 can be coupled to ground. In response to another phase (a“high” level) of clock signal CLK during operation of charge pump 310, the bottom plate of capacitor Cl can be coupled to ground, and the bottom plate of capacitor C2 can be coupled to node 305 (to voltage VPH). The operation of switching circuit 311, capacitors Cl and C2, and diodes Dl, D2, and D3 allow charge pump 310 to generate voltage VOUT that can have a value greater than the value of voltage VIN (e.g., VOUT > VIN). FIG. 3 shows an example of a positive charge pump 310. However, the techniques described herein can also be applicable to a negative charge pump (e.g., VOUT < VIN).

[0052] Output regulator 320 can include a source follower output stage

(e.g., included in operational amplifier 321) to generate voltage VREG OUT based on voltages VOUT and VBG. Voltage VREG DUT is the regulated voltage of VOUT.

[0053] Current sensor 341 can operate to generate a current ISENSE based on current IQUT. Current ISENSE can be a scaled down replica of current IOUT. For example, the value of ISENSE can be less than the value of current IOUT by a factor X (e.g., ISENSE = IOUT / X, where X is a positive real number).

[0054] Current to voltage converter 342 can operate to convert a current

IREF into a voltage VREF. Current IREF can be a scaled down replica of current ISENSE. For example, the value of IREF can be less than the value of current ISENSE by a factor M (e.g., IREF ^::: ISENSE / M, where M is a positive real number). In FIG. 3, transistors P3 and P4 can be arranged to form a current mirror circuit such that IREF = ISENSE / M, where M can be the size ratio of transistors P3 and P4. Using a scaled down value of current IOUT can reduce power consumption of current sensor 341 and current to voltage converter 342.

[0055] The value of voltage VREF generated by current to voltage converter 342 is function of (e.g., based on) the value of current IREF and resistor RREF and the value of a voltage (e.g., VD) across diode D. The value of voltage VREF can be less than the value of voltage VIN (e.g., VREF < VIN). Diode D can have the same structure as diode Dl, D2, and D3 (e.g., the same as the charge transfer switch of charge pump 310). This helps reduce the influence of the process technology and temperature on the feedback mechanism (e.g., monitor circuit that includes voltage converter 342). Current source 343 is included in voltage generator 301 to provide a current through resistor R _REF and diode D.

The inclusion of current source 343 ensures that equation (1) satisfies the following condition.

[0056] [C/(C + Cs)] * VPH -Vo > 0 (9)

[0057] Satisfying the condition as shown in equation (9) allows voltage

VREF to be at a safe level in order to maintain proper functionality of charge pump 310.

[0058] Phase supply voltage controller 330 can include a voltage follower output circuit (e.g., included in operational amplifier 331) to generate voltage VPH based on voltage VREF (e.g., VPH = VREF). AS shown in FIG. 3, voltage VPH can be provided to switching circuit 311 (e.g., provided to the sources of transistors PI and P2) of charge pump 310 and can be used as supply voltage for switching circuit 311. As described above, the value of voltage VPH can be adjusted based on the value of current lour (e.g., the value of voltage VPH is reduced when the value of current IQUT decreases) in order improve the efficiency and quality of voltage VOUT of charge pump 310. Voltage generator 301 of FIG. 3 can include improvements and benefits similar to those of voltage generator 101 described above with reference to FIG. 1 and FIG. 2.

[0059] FIG. 4 shows an apparatus in the form of a system (e.g., electronic system) 400, according to some embodiments described herein.

System 400 can include or be included in a computer, a tablet, or other electronic systems. As shown in FIG. 4, system 400 can include components such as a battery 405, a processor 415, a memory device 420, a memory controller 430, a graphics controller 440, an input and output (I/O) controller 450, a display 452, a keyboard 454, a pointing device 456, at least one antenna 458 and an antenna circuit path (e.g., antenna signal path) 402, a connector 459, and a bus 460. Bus 460 can include conductive lines (e.g., metal-based traces on a circuit board where the components of system 400 are located).

[0060] In some arrangements, system 400 does not have to include a display. Thus, display 452 can be omitted from system 400. In some arrangements, system 400 does not have to include any antenna. Thus, antenna 458 can be omitted from system 400. [0061] Battery 405 can provide power to the components of system 400,

(e.g., through a power delivery path 416) such as to processor 415, memory device 420, memory controller 430, graphics controller 440, and I/O controller 450.

[0062] Processor 415 can include a general-purpose processor or an application specific integrated circuit (ASIC). Processor 415 can include a CPU.

[0063] Memory device 420 can include a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, a flash memory device, a phase change memory device, a combination of these memory devices, or other types of memory. FIG. 4 shows an example where memory device 420 is a stand-alone memory device separated from processor 415. In an alternative arrangement, memory device 420 and processor 415 can be located on the same die. In such an alternative arrangement, memory device 420 is an embedded memory in processor 415, such as embedded DRAM

(eDRAM), embedded SRAM (eSRAM), embedded flash memory, or another type of embedded memory.

[0064] Display 452 can include a liquid crystal display (LCD), a touchscreen (e.g., capacitive or resistive touchscreen), or another type of display. Pointing device 456 can include a mouse, a stylus, or another type of pointing device.

[0065] I/O controller 450 can include a communication module for wired or wireless communication (e.g., communication through one or more antennas 458). Such wireless communication may include communication in accordance with WiFi communication technique, Long Term Evolution Advanced (LTE-A) communication technique, or other communication techniques.

[0066] I/O controller 450 can also include a module to allow system 400 to communicate with other devices or systems in accordance with one or more standards or specifications (e.g., I/O standards or specifications), including Universal Serial Bus (USB), DisplayPort (DP), Fligh-Defmition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), Ethernet, and other specifications.

[0067] Connector 459 can be arranged (e.g., can include terminals, such as pins) to allow system 400 to be coupled to an external device (or system). This may allow system 400 to communicate (e.g., exchange information) with such a device (or system) through connector 459.

[0068] Connector 459 and at least a portion of bus 460 can include conductive lines that conform with at least one of USB, DP, HDMI,

Thunderbolt, PCIe, Ethernet, and other specifications.

[0069] As shown in FIG. 4, each of processor 415, memory device 420, memory controller 430, graphics controller 440, and I/O controller 450 can include a voltage generator 401. Voltage generator 401 can include voltage generator 101 and voltage generator 301 described above with reference to FIG.

1 through FIG. 3. Thus, voltage generator 401 can include a charge pump, an output regulator, a phase supply voltage controller, and a monitor circuit that includes a current sensor and a current to voltage converter described above with reference to FIG. 1 through FIG. 3.

[0070] As shown in FIG. 4, system 400 can also include voltage generator 401 to provide a voltage V _RE G_OU _T to antenna circuit path 402.

Antenna circuit path 402 can include transistors (not shown) that can operate as switches to control signals (e.g., signals received from antenna 458) on antenna circuit path 402. Voltage VREG OUT provided antenna circuit path 402 can be used to control the gates of the transistors of antenna circuit path 402, to provide voltage to the bulks of the transistors of antenna circuit path 402, or both. Using voltage VREG OUT from voltage generator 401 to control signals (control the propagation of signals) in antenna circuit path 402 can avoid injection of noise into antenna circuit path 402. Thus, signal integrity on antenna circuit path 402 can be maintained.

[0071] FIG. 4 shows an example where each of processor 415, memory device 420, memory controller 430, graphics controller 440, and I/O controller 450 includes voltage generator 401. However, in some arrangements, some of processor 415, memory device 420, memory controller 430, graphics controller 440, and I/O controller 450 may not include generator 401.

[0072] FIG. 4 shows the components of system 400 arranged separately from each other as an example. For example, each of antenna circuit path 402, processor 415, memory device 420, memory controller 430, graphics controller 440, and I/O controller 450 can be located separately in system 400. For example, each of these components can be located on an integrated circuit (1C) (e.g., semiconductor die or an IC chip). In some arrangements, two or more components (e.g., antenna circuit path 402, processor 415, memory device 420, graphics controller 440, and I/O controller 450) of system 400 can be located on the same die (e.g., same IC chip) that forms a system-on-chip (SoC) or located on the same IC package that forms a system-on-package (SoP) or system-in- package (SiP).

[0073] The illustrations of the apparatuses (e.g., apparatuses 100 and 300 and system 400 including voltage generators 101, 301, and 401) described above are intended to provide a general understanding of the structure of different embodiments and are not intended to provide a complete description of all the elements and features of an apparatus that might make use of the structures described herein.

[0074] The apparatuses and methods described above can include or be included in high-speed computers, communication and signal processing circuitry, single-processor modules or multi-processor modules, single embedded processors or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multilayer or multi-chip modules. Such apparatuses may further be included as sub-components within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, etc.), tablets (e.g., tablet computers), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set top boxes, and others.

Additional Notes and Examples

[0075] Example 1 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including a first node to receive a first supply voltage, a second node receive a second supply voltage, a third node to receive a clock signal, a charge pump coupled the first, second, and third nodes to generate an output voltage based on the first supply voltage, the second supply voltage, and timing of the clock signal, an output regulator to generate a voltage at a node based on the output voltage, and a monitor circuit to monitor an output current at the node and provide feedback information based on the output current to adjust a value of the second supply voltage

[0076] In Example 2, the subject matter of Example 1 may optionally include, wherein the monitor circuit is to generate a reference current based on the output current, and the feedback information includes a reference voltage generated based on the reference current.

[0077] In Example 3, the subject matter of Example 1 or 2 may optionally include, further comprising a controller to adjust the value of the second suppl y voltage based on a value of the reference voltage.

[0078] In Example 4, the subject matter of Example 1 or 2 may optionally include, wherein the charge pump includes an output node to provide the output voltage, and at least one diode coupled between the first node and the output node.

[0079] In Example 5, the subject matter of Example 4 may optionally include, wherein the charge pump includes a driver coupled between the second node and ground.

[0080] In Example 6, the subject matter of Example 5 may optionally include, wherein the driver includes transistors having gates coupled to the third node.

[0081] In Example 7, the subject matter of Example 1 may optionally include, wherein a value of the second supply voltage is less than a value of the first supply voltage.

[0082] Example 8 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including a charge pump to generate an output voltage at an output node based on a first voltage, the charge pump including a switching circuit to control generation of the output voltage based on timing of a clock signal, the switching circuit including a node to receive a second voltage, an output regulator to generate a regulated output voltage based on the output voltage and provide the regulated output voltage at a regulator output node, a current sensor to generate a reference current based on an output current at the regulator output node, a converter to convert the reference current into a reference voltage, and a controller to control the second voltage based on the reference voltage.

[0083] In Example 9, the subject matter of Example 8 may optionally include, wherein the charge pump includes an input node to receive the first voltage, and diodes connected in series between the input and output nodes.

[0084] In Example 10, the subject matter of Example 9 may optionally include, wherein the charge pump includes a driver coupled to the node of the switching circuit, and a capacitor coupled between one of the diodes and an output node of the driver.

[0085] In Example 11, the subject matter of Example 10 may optionally include, wherein the charge pump includes an additional driver coupled to the node of the switching circuit, and an additional capacitor coupled between one of the diodes and an output node of the additional driver.

[0086] In Example 12, the subject matter of Example 11 may optionally include, wherein each of the driver and the additional driver includes transistors having gates to receive the clock signal.

[0087] In Example 13, the subject matter of any of Examples 8-12 may optionally include, wherein the current sensor includes a first transistor and a second transistor coupled between the output node of the charge pump and the regulator output node.

[0088] In Example 14, the subject matter of any of Examples 8-12 may optionally include, wherein the converter includes a transistor, a resistor, and a diode coupled between the output node of the charge pump and ground.

[0089] In Example 15, the subject matter of Example 14 may optionally include, wherein the charge pump includes an input node to receive the first voltage, and the converter includes a current source coupled between the input node and the resistor.

[0090] In Example 16, the subject matter of Example 8 may optionally include, wherein the controller includes a voltage follower circuit to adjust a value of the second voltage based on a value of the reference voltage.

[0091] Example 17 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including an antenna circuit path, and a voltage generator coupled to the antenna circuit path, the voltage generator including a first node to receive a first supply voltage, a second node receive a second supply voltage, a third node to receive a clock signal, a charge pump coupled to the first, second, and third nodes to generate an output voltage based on the first supply voltage, the second supply, and timing of the clock signal, an output regulator to generate a voltage at a node based on the output voltage, and a monitor circuit to monitor an output current at the node and provide feedback information based on the output current to adjust a value of the second supply voltage.

[0092] In Example 18, the subject matter of Example 17 may optionally include, further comprising a connector coupled to the processor, the connector conforming with one of Universal Serial Bus (USB), High-Definition

Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), and Ethernet specifications.

[0093] In Example 19, the subject matter of Example 17 or 18 may optionally include, further comprising a processor coupled to the antenna circuit path.

[0094] In Example 20, the subject matter of Example 17 or 18 may optionally include, further comprising a display coupled to the antenna circuit path.

[0095] The subject matter of Example 1 through Example 20 may be combined in any combination.

[0096] In the detailed description and the claims, a list of items joined by the term“one of’ can mean only one of the listed items. For example, if items A and B are listed, then the phrase“one of A and B” means A only (excluding B), or B only (excluding A). In another example, if items A, B, and C are listed, then the phrase“one of A, B, and C” means A only, B only, or C only. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0097] In the detailed description and the claims, a list of items joined by the term“at least one of” can mean any combination of the listed items. For example, if items A and B are listed, then the phrase“at least one of A and B” means A only, B only, or A and B. In another example, if items A, B, and C are listed, then the phrase“at least one of A, B, and C” means A only; B only; C only; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0098] The above description and the drawings illustrate some embodiments to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations.

Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the scope of various embodiment s is determined by the appended claims, along with the full range of equivalents to which such claims are entitled.

[0099] The Abstract is provided to comply with 37 C.F.R. Section

1.72(b) requiring an abstract that will allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.