Title:
CHIP ARCHITECTURE RECONSTRUCTION METHOD AND APPARATUS, AND COMPUTER READABLE STORAGE MEDIUM
Document Type and Number:
WIPO Patent Application WO/2018/010520
Kind Code:
A1
Abstract:
A chip architecture reconstruction method, comprising: providing a programmable circuit in an ASIC, and setting a configuration file set consisting of configuration files corresponding to different scenes of the programmable circuit (101); determining a current scene where the ASIC operates, and obtaining a configuration file corresponding to the current scene from the configuration file set according to the current scene (102); and configuring the programmable circuit using the configuration file corresponding to the determined current scene (103). Also disclosed are a chip architecture reconstruction apparatus and a computer readable storage medium.
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Inventors:
WEI GUOQING (CN)
WANG YONG (CN)
WANG YONG (CN)
Application Number:
PCT/CN2017/088652
Publication Date:
January 18, 2018
Filing Date:
June 16, 2017
Export Citation:
Assignee:
SANECHIPS TECH CO LTD (CN)
International Classes:
G06F15/78
Foreign References:
| CN101573703A | 2009-11-04 | |||
| CN101420371A | 2009-04-29 | |||
| CN105205034A | 2015-12-30 | |||
| US8476926B1 | 2013-07-02 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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