Title:
CHIP ENCAPSULATION PROCESS
Document Type and Number:
WIPO Patent Application WO/2022/179296
Kind Code:
A1
Abstract:
Disclosed in the present application is a chip encapsulation process, comprising the steps of: providing a wafer module, wherein the wafer module comprises a wafer and a first sticking film, the wafer has a plurality of chips, back faces of the chips are stuck to the first sticking film, and front faces of the chips are provided with a plurality of bumps arranged at intervals; providing an adhesive film, wherein the adhesive film has a conductive adhesive layer and a non-conductive adhesive layer which are arranged in a stacked manner, the adhesive film is attached to the front faces of the chips, and the bumps are embedded in the non-conductive adhesive layer, such that the bumps are in contact with the conductive adhesive layer; separating the chips, and disconnecting the conductive adhesive layer on the chips in correspondence with the bumps; and attaching the chips onto a substrate, such that the conductive adhesive layer is connected to pads on the substrate, so as to form a conductive structure, and the non-conductive adhesive layer encapsulates the conductive structure.
Inventors:
YU SHANGJIA (CN)
JIANG ZHONGHUA (CN)
SU MINGHUA (CN)
WANG JUNHUI (CN)
JIANG ZHONGHUA (CN)
SU MINGHUA (CN)
WANG JUNHUI (CN)
Application Number:
PCT/CN2021/143037
Publication Date:
September 01, 2022
Filing Date:
December 30, 2021
Export Citation:
Assignee:
QINGDAO GOERTEK MICROELECTRONICS RES INSTITUTE CO LTD (CN)
International Classes:
H01L21/48; H01L21/67
Foreign References:
| CN113161242A | 2021-07-23 | |||
| CN101689513A | 2010-03-31 | |||
| US20130065362A1 | 2013-03-14 | |||
| US20080277802A1 | 2008-11-13 | |||
| CN103137611A | 2013-06-05 | |||
| US6518097B1 | 2003-02-11 |
Attorney, Agent or Firm:
CENFO INTELLECTUAL PROPERTY AGENCY (CN)
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