Title:
CHIP ESD PROTECTION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/215015
Kind Code:
A1
Abstract:
A chip ESD protection circuit, comprising an integrated circuit layer and a conductive layer (1), wherein first ground pads (21, 23) connected to a first ground line (31) of a first power domain (51) are respectively arranged on the first power domain (51) and a second power domain (52) in the integrated circuit layer, and the first ground pads (21, 23) are bonded onto the conductive layer (1); a second power clamp unit (62) is arranged on the second power domain (52), a first end of the second power clamp unit (62) is connected to a second power line (33) of the second power domain (52), and a second end thereof is connected to the first ground line (31) or a second ground line (34) of the second power domain (52); and a bi-directional ESD protection circuit (8) is further arranged on the second power domain (52), and the bi-directional ESD protection circuit (8) is arranged between the first ground line (31) and the second ground line (34). The ESD protection capability of a chip can be improved, and the layout area of the chip can be reduced.
Inventors:
WANG YAN (CN)
LIU TAO (CN)
CHEN GUANGBING (CN)
WANG YUXIN (CN)
FU DONGBING (CN)
YANG YUJUN (CN)
CHEN LIANG (CN)
PU YANG (CN)
LIU TAO (CN)
CHEN GUANGBING (CN)
WANG YUXIN (CN)
FU DONGBING (CN)
YANG YUJUN (CN)
CHEN LIANG (CN)
PU YANG (CN)
Application Number:
PCT/CN2016/086643
Publication Date:
December 21, 2017
Filing Date:
June 22, 2016
Export Citation:
Assignee:
CHINA ELECTRONIC TECH CORPORATION 24TH RESEARCH INSTITUTE (CN)
International Classes:
H05F3/02; H02H9/00
Foreign References:
| CN1930676A | 2007-03-14 | |||
| CN104347621A | 2015-02-11 | |||
| US20060189189A1 | 2006-08-24 | |||
| US20050052799A1 | 2005-03-10 | |||
| US20030039084A1 | 2003-02-27 |
Attorney, Agent or Firm:
BEIJING YIGE INTELLECTUAL PROPERTY AGENT LTD(GENERAL PARTNERSHIP) (CN)
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