Integrated circuits, also known as"chips,"are complex electronic devices containing many components. The performance of these circuits as well as the presence or absence of errors depends on the manufacturing process used to make them. Design features such as the resistance of a particular circuit path, the gain of an amplifier or the amount of charge that can be stored on a capacitor can change significantly with only a small variation in the process used to produce the integrated circuit.

Typically, integrated circuits are made on wafers of silicon. Current processes use wafers ranging in size from three to 12 inches in diameter.

Integrated circuits are made by a photolithographic process in which a photosensitive masking material is applied to the wafer, a pattern of light is formed on the wafer which polymerizes the masking material only in the exposed areas, the unexposed masking material is removed and the exposed portions of the wafer are"doped"with an impurity that changes the electrical properties of the semiconductor material. Typically, integrated circuits are formed using several mask and dope cycles in addition to other processes such as oxide growth, chemical vapor deposition (CVD) and ion implantation.

Multiple integrated circuits are formed on a single wafer in a matrix arrangement using either a single set of masks for the entire wafer, each mask in the set defining the same step for all of the integrated circuits on the wafer, or by stepping each mask of a single set masks that defines only one integrated circuit, across the surface of the wafer.

As described above, the performance of the integrated circuits depends strongly on the process. Slight variations in the process such as applying dopants in different concentrations can change the performance of otherwise identical integrated circuits from wafer to wafer. In addition, process variations can occur across a single wafer. If, for example, the concentration of a dopant changes with the position on the wafer, integrated circuits formed in different positions on the wafer will exhibit different characteristics. Furthermore, when integrated circuits are made from a set of masks that cover the entire wafer, an imperfection in any individual mask at any one position can cause the integrated circuit formed at that position on the wafer to operate incorrectly.

Not all imperfections in integrated circuits, however, are spatially or temporally related. Random errors such as dislocation defects in the single- crystal wafer or pinhole defects in an oxide coating cause random failures in the manufactured integrated circuits.

The yield of an integrated circuit process is the number of good devices divided by the total number of devices made. The profitability of a particular integrated circuit is strongly related to the yield of the process. While random errors can be reduced, they can not be eliminated. Many position-related errors, however, can be eliminated. To find these wafer-related and position-related defects, many integrated circuit manufacturers include a small programmable memory on each integrated circuit that they manufacture which identifies the manufacturing lot, the particular wafer and the position on the wafer of the integrated circuit.

This information may be programmed into the particular integrated circuit by a fusing process that uses a laser beam to physically open or"blow" metallic or polysilicon fuses. For example, if a fuse has not been blown open, it may represent a binary zero, if it has been blown, it may represent a binary one.

The fuses are arranged on the integrated circuits in"fuse banks."One fuse bank corresponds to the chip identification information.

Alternatively, identified information may be held in an electrically programmable memory (EPROM) or a mask programmable memory. If a mask programmable memory is used, a different mask would be used for each integrated circuit on the wafer during the manufacturing process. The information is typically read from the integrated circuit by applying signal levels that would be invalid during normal operation. For example, if the integrated circuit were a memory chip, each address in the address sequence may simultaneously activate both the write enable (WE) signal and the row address strobe (RAS) signals. In a typical memory device, RAS would be activated first to set the address in the memory and then WE would be activated to write the data into the memory. In addition, a specific sequence of address values is applied to the integrated circuit. The identification data provided by the integrated circuit is typically encoded such that, even if a competitor discovers the address sequence needed to read the data, the recovered data is meaningless.

When defective circuits are found during factory testing, the identification information is recovered and used to locate problems with the masks or with the manufacturing equipment. Factory testing uses equipment that is both large and expensive, as it performs a complete functional test of the circuit.

In a production environment, there are situations where the lot identifier of a particular integrated circuit is needed. Due to manual handling of component trays, integrated circuits from one lot may be mixed with circuits from another lot. The normal procedure for obtaining the lot identifier is to place the integrated circuits into a test system and read out the programmed identification information. This procedure is disadvantageous because of the time needed to load the components into the tester. It may take, for example, five minutes or more to obtain this information. While these integrated circuits are being tested, the system is blocked and the normal production process stops.

Integrated circuit identification information may also be lost during environmental testing. Typically, environmental testing laboratories do not include factory testing equipment. Because environmental testing generally involves manual handling of the integrated circuits, human error can result in integrated circuits having unknown identification information.

SUMMARY OF THE INVENTION The present invention is embodied in a portable electronic device that includes an integrated circuit socket into which an unidentified integrated circuit may be placed. The device also includes a controller which applies an address sequence to the integrated circuit to read its identification information.

The device then displays the identification information to the user.

According to one aspect of the invention, the device includes a switch which is activated to test the integrated circuit only when the circuit is inserted in the socket and the controller selectively applies power to the integrated circuit only when the test switch is pressed.

According to another aspect of the invention, the device includes a memory which temporarily stores the identification information and a communications interface through which this information may be up-loaded to a host computer.

According to yet another aspect of the invention, the device includes test routines for several integrated circuit types and allows the technician to select a particular integrated circuit type before retrieving the identification information.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram, partly in schematic diagram form, of an integrated circuit identification reader which includes an embodiment of the present invention.

Figure 2 is a high-level flow-chart diagram of a program which may control the reader shown in Figure 1.

Figure 3 is a flow-chart diagram of an exemplary identification reading process shown in Figure 2.

Figure 4 is a schematic diagram, partly in block diagram form, of an exemplary implementation of an integrated circuit reader which processes only a single type of integrated circuit.

DETAILED DESCRIPTION Figure 1 is a block diagram of circuitry suitable for use as the chip identification reader. The circuitry includes a processing module 100 which, in the exemplary embodiment of the invention, is a Basic Stamp controller available from Parallax, Inc. The exemplary reader also includes an integrated circuit socket 110, a display device 112 and a power supply 115 (e. g. a nine- volt battery). In the exemplary embodiment of the invention, an integrated circuit (not shown) that is to be read is inserted into the socket 110.

The exemplary processing module includes a regulated power supply 156 which is coupled to receive operational power from the power supply 115 via a power switch 114, to provide an operational potential (e. g. five volts) and a reference potential (e. g. ground) to the remainder of the processing module 100 and to the display device 112.

The exemplary processing module 100 also includes a processor 150, an electronically erasable programmable read only memory (EEPROM) 152 and a communications interface 154. The processing module includes a number of input/output (I/O) pins which can be controlled to provide signal values (e. g. five volts or ground) to, or to receive signal values from the integrated circuit that is inserted in the socket 110. One I/O pin of the processor 150 is coupled to receive either five volts or ground via a momentary contact start switch 120.

As described below, this switch may be used to select a particular integrated circuit type to be interrogated or to begin reading the identification information from an integrated circuit of the selected type.

The exemplary EEPROM 152 receives and stores program instructions and associated data from an external host computer (not shown, e. g. a laptop computer or a personal digital assistant). The program instructions and any data associated with them are provided to the processor 150 via the communications interface 154. In the exemplary embodiment of the invention, the communications interface is an RS 232 serial communications interface.

The exemplary processing module 100 also includes a boot loader which automatically loads and stores the program provided by the host computer into the EEPROM 152. In addition, the RS 232 interface may be used to upload data from the processing module 100 to the host computer.

In a factory environment, the chip identification reader may be limited to processing only one type of integrated circuit. In this situation, the test program may be downloaded into the EEPROM 152 only once, during initial configuration. After this initial downloading, the communications interface 154 may be used only to upload data read from the integrated circuits to the host computer.

As described below, the computer program causes the processor to prompt the user at various points in the process by displaying information on the display 112. In the exemplary embodiment of the invention, the display is a one-line liquid crystal device (LCD) display which can display, for example, 16 alphanumeric characters.

In the exemplary embodiment of the invention, pins of the integrated circuit held in the socket 110 are either coupled to ground or to one of the I/O pins of the processor 150. Even the operational power signal is provided, to the integrated circuit being read, through the processor 150. This is done to limit the current that can be applied to the integrated circuit as well as to control the application of power to the integrated circuit in order to ensure that the results are valid and the integrated circuit is not damaged as it is being inserted into the reader. In addition, by applying operational power to the integrated circuit only when it is needed, the controller limits the current drain on the battery, increasing its life.

Figures 2 and 3 are flow-chart diagrams which illustrate an exemplary program flow for the processor 150 as it is reading the identification information from the integrated circuit. The program shown in Figure 2 is automatically executed immediately after it is loaded into the EEPROM 152 or, if the program is already stored in the EEPROM 152, immediately after power is applied to the reader via the power switch 114.

The exemplary program shown in Figures 2 and 3 allows identification information to be read from different chip types. The reader may be programmed to read several devices which have the same form factor or can be inserted into the socket 110. It is contemplated, however, that the device may read information from only a single chip type. In this instance, the section of the program flow shown in Figure 2 would not be implemented in the reader.

The first step of the program shown in Figure 2 is to display a first device type and wait two seconds for the user to press the start switch 120. If, at step 212, the start switch has not been pressed in the two seconds since the first device type was displayed, the program executes step 214 which displays the next device type for two seconds and waits for the user to press the start button. The device types are arranged in a circular queue so that, after the reader cycles through all of the device types that it can test, it begins, again, with the first device type.

If, at step 212, the start switch is engaged, control transfers to step 216 which executes the identification routine for the selected device type. An exemplary identification routine is described below with reference to Figure 3.

After completing the test and presenting the data to the user, the process, at step 217 displays the identification data, waits two seconds, and displays"ID recorded ?" At step 219, the process continually loops on these two steps until the user engages the start switch. After step 219, the process displays the device type that was just tested and, if the user engages the start switch 120 within two seconds, control returns to step 216 to re-run the reading process that was just executed. Otherwise, control transfers to step 212 to display the list of device types that can be tested.

Figure 3 is a flow-chart diagram of an exemplary reading process, such as the process 216 shown in Figure 2. In the process shown in Figure 3, after each step in which signal values are applied to the chip being read, the controller 100 asserts the clock signal to five volts and then to ground to simulate applying a clock pulse to the chip.

The first step in this process, step 300 displays the message,"Begin Test ?" to the user. At step 310, when the user presses the start button, the reading process begins. The first step in the process, step 312, precharges the input terminals of the chip and applies operational power. As set forth above, the exemplary identification reader applies operational power to the integrated circuit via one of the I/O terminals of the controller. This is done to prevent damage to the integrated circuit, by limiting the current that can be drawn by the chip and ensuring that all pins of the socket 110 are either disconnected or grounded as the chip is inserted. In addition, by applying operational power using its I/O pins, the controller 100 can conserve battery power and ensure that the integrated circuit is in a known initial state at the start of the reading operation.

Next, at step 314, the controller assigns values to the pins that do not change as the sequence of addresses are applied. In the exemplary embodiment of the invention described below, the addresses in the address sequence use the chip select (CS), RAS and WE signals as well as the address input signals. At step 316, the controller 100 enters the address sequence which causes the integrated circuit to provide its identification information. At step 318, the controller 100 reads the identification information that is provided by the chip.

Next, at step 320, the controller 100 grounds the I/O terminal that is connected to the operational power pins of the integrated circuit, removing operational power from the chip. At step 322, the controller decodes the data read from the integrated circuit to obtain the wafer identifier and to obtain the X and Y coordinates of the integrated circuit die as it was formed on the wafer. At step 324, the process displays the result to the user. If the tester is configured to test only a single device type then, after step 324, control is transferred to step 300 as shown by the dashed-line arrow. Otherwise, control transfers to step 220 of Figure 2.

In one exemplary embodiment of the invention, the controller 100 may store the identification data read from a particular chip either in random-access memory internal to the processor 150 or in the EEPROM 152. This data may then be uploaded to the host computer via the communications link 154. In one embodiment of the invention, the reader is coupled to a wireless communications link and transits the identification information to the host computer as it is retrieved. It is contemplated that the identification information sent to the host computer may be in either encoded or decoded form.

Figure 4 is a schematic diagram of an exemplary embodiment of the chip identification reader that is configured to read the identification information from a memory chip. The exemplary reader includes the controller 100, chip socket 110, LCD display 112, serial communications port 128, power switch 114, battery 115 and start switch 120. In addition, the circuit includes a light- emitting diode (LED) 118 and a series of jumpers 130. The start switch 120 is in series with a resistor 122 to limit current flow when the switch is activated.

The active-low reset pin of the controller 100 is coupled to a resistor 123 which is coupled to the five volt power supply. In this configuration, the tester is reset only when power is first applied to the controller 100. A resistor 118 is in series with the LED 116 to limit the current flow while the LED 116 is illuminated. Finally, the circuit shown in Figure 126 includes a bypass capacitor 126 to attenuate voltage spikes on the operational power signal that is applied to the integrated circuit.

As shown in Figure 4, all of the operational power (VDD and VDDQ) pins of the socket 110 and the clock enable (CKE) pin are coupled to I/O pin 11 of the controller 100 while all of the reference potential pins (VSS and VSSQ) are coupled to ground. I/O pin 11 of the controller 100 is also coupled to one side of the jumpers 130 and to the series-connected resistor 118 and LED 116. Thus, in the interval between steps 312 and 320 of Figure 3, while the reader is applying power to the integrated circuit, the LED 116 is lit.

The chip select (CS) pin of the integrated circuit is coupled to I/O pin 13 of the controller 100, the row address strobe (RAS) pin is coupled to I/O pin 8, the write enable (WE) pin is coupled to I/O pin 14 and the column address strobe (CAS) signal and bit 10 of the data address (A10) are coupled to I/O pin 6 of the controller. The integrated circuit address bits 0 through 5 (A0, A1, A2, A3, A4 and A5) are coupled to I/O pins 0 through 5 of the controller 100. The clock pin of the integrated circuit is coupled to I/O pin 7 of the controller 100.

The remaining address pins are coupled to either five volts or ground via the jumpers 130. In the exemplary embodiment of the invention, the entry key consists of three different addresses. Each address is a 14-bit binary number.

Some of these bits do not change for the three entry keys. Because the exemplary controller includes only a limited number (e. g. 16) of I/O channels, the jumpers 130 are used to set the address bits of the entry keys that do not change. The setting of these jumpers depends on the address values that are used to access the identification information and would be known to the manufacturer of the integrated circuit. When the tester is configured to process more than one type of integrated circuit, the jumpers 130 may be controlled three-state switches which are set by the controller (not shown) in order to configure these address pins to read the identification data.

In the exemplary embodiment of the invention, the address sequence to obtain the identification codes is entered by applying control signals to the CS, RAS and WE pins, via I/O pins 13,8 and 14, respectively and then cycling the CAS and address pins via I/O pins 0 through 6. The identification data is read as 11 bit-serial bytes provided via pin DQ 13 of the integrated circuit, which is coupled to I/O pin 9 of the controller 100.

This address data is decoded by the processor 150 into a lot number, a split number, a wafer number and the X and Y coordinates of the integrated circuit die on the wafer. These values are then displayed to the operator on the LCD display 112.

Although the invention has been described in terms of an exemplary embodiment, it is contemplated that it may be practiced as described above within the scope of the appended claims.