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Title:
CHIP PACKAGING STRUCTURE AND METHOD
Document Type and Number:
WIPO Patent Application WO/2020/103748
Kind Code:
A1
Abstract:
A chip packaging structure and method. A package substrate (12) having a through hole (T) is used for packaging a chip; a first chip (11) is disposed in the through hole (T); the first chip (11) and the package substrate (12) are fixed by means of a first plastic packaging layer (13); a second surface of the packaging substrate (12), the back surface of the first chip (11), and the first plastic packaging layer (13) in the through hole (T) are covered by a second plastic packaging layer (14). Thus, a package structure is formed, and the device has a simple structure. The first chip (11) can be electrically connected to an external circuit by means of a first contact end (121) of the package substrate (12), so that the first chip (11) is electrically connected to the external circuit. Moreover, the first chip (11) and the first plastic packaging layer (13) in the through hole (T) are borne by means of the second plastic packaging layer (14); when the side of the package structure close to the front surface of the first chip (11) is under pressure, the second plastic packaging layer (14) can buffer the pressure, thereby avoiding the problem of failure at the junction of the back periphery of the first chip (11) and the second plastic packaging layer (14) due to the pressure.

Inventors:
WANG ZHIQI (CN)
ZHANG CHENG (CN)
Application Number:
PCT/CN2019/118170
Publication Date:
May 28, 2020
Filing Date:
November 13, 2019
Export Citation:
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Assignee:
CHINA WAFER LEVEL CSP CO LTD (CN)
International Classes:
H01L21/56; H01L23/31; H01L23/488
Foreign References:
CN109494163A2019-03-19
CN108447842A2018-08-24
CN108257921A2018-07-06
CN101587847A2009-11-25
CN106415823A2017-02-15
US20080157342A12008-07-03
Attorney, Agent or Firm:
BEYOND ATTORNEYS AT LAW (CN)
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