CHIP PACKAGING STRUCTURE AND CHIP PACKAGING METHOD

WIPO Patent Application WO/2020/232610

A1

A chip packaging structure and a chip packaging method. The chip packaging structure comprises at least a first chip (10), a second chip (20), and a bearing plate (30), wherein the first chip (10) is disposed between the second chip (20) and the bearing plate (30), the active layer (101) of the first chip (10) is opposite to the active layer (201) of the second chip (20), and a first interconnection structure (102) for connecting the active layer (101) of the first chip (10) and the active layer (201) of the second chip (20) is provided between the first chip (10) and the second chip (20); a first conductor post (103) is provided inside the first chip (10); one end of the first conductor post (103) is connected to the active layer (101) of the first chip (10), and the other end of the first conductor post (103) passes through the first chip (10) and is connected to the circuit in the bearing plate (30). By connecting the active layers of the two chips oppositely, the route of signal transmission between the two chips is shortened, and the efficiency of signal transmission between the two chips is improved.

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ZHANG TONGLONG (CN)
ZHANG XIAODONG (CN)
GUAN YONG (CN)
LI HENG (CN)

PCT/CN2019/087659

November 26, 2020

May 20, 2019

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HUAWEI TECH CO LTD (CN)

H01L25/065; H01L23/498

CN104253056A	2014-12-31
CN104253056A	2014-12-31
CN2636411Y	2004-08-25
CN107731761A	2018-02-23
CN105374793A	2016-03-02
CN107808878A	2018-03-16

See also references of EP 3958307A4

SCIHEAD IP LAW FIRM (CN)

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