CHIP-RESISTOR MANUFACTURING METHOD

Title:

CHIP-RESISTOR MANUFACTURING METHOD

Document Type and Number:

WIPO Patent Application WO/2015/008679

Kind Code:

A1

Abstract:

This invention provides a chip-resistor manufacturing method that inhibits chipping at intersections where primary segmentation grooves and secondary segmentation grooves intersect. Primary segmentation grooves (21) that have a certain asperity depth are formed in one surface of a large substrate (20), and after a plurality of pairs of surface electrodes (3) that straddle said primary segmentation grooves (21) and resistive elements (5) and the like that straddle pairs of said surface electrodes (3) are formed, primary segmentation is performed on the large substrate (20) along the primary segmentation grooves (21) as though to open same on the side where the surface electrodes (3) and the resistive elements (5) and the like are formed. A plurality of strip-shaped substrates (30) are thus obtained from the large substrate (20). During the primary segmentation, the fracturing of the primary segmentation grooves (21) starts in the electrode-formation regions, which are stronger due to the grooves being more shallow there, and only after that does segmentation occur in the abovementioned intersections, which are more brittle due to the grooves being deeper there. The primary segmentation can thus be performed without large loads being applied to the weak intersections, preventing chipping at said intersections.

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Inventors:

TAKEUE YUYA (JP)
UEGANE TOTARO (JP)
MATSUMOTO KENTARO (JP)

Application Number:

PCT/JP2014/068350

Publication Date:

January 22, 2015

Filing Date:

July 09, 2014

Export Citation:

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Assignee:

KOA CORP (JP)

International Classes:

H01C17/06

Foreign References:

JP2007165517A	2007-06-28
JP2003086408A	2003-03-20
JPH0687085A	1994-03-29
JPH0677001A	1994-03-18

Attorney, Agent or Firm:

The Patent Body Corporate TAKEWA INTERNATIONAL PATENT OFFICE (JP)
Patent business corporation Takekazu international patent firm (JP)

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