CHIP STACK PACKAGING STRUCTURE AND CHIP STACK PACKAGING METHOD

WIPO Patent Application WO/2023/010457

A1

The present application relates to a chip stack packaging structure and a chip stack packaging method capable of achieving chip stack packaging with low cost and high accuracy. The packaging structure comprises: a substrate chip layer comprising a substrate chip having pins on the front surface; at least one stacked chip layer sequentially formed on the substrate chip layer, and comprising an inter-chip insulating layer and at least one stacked chip attached to the inter-chip insulating layer and having a plurality of pins on the front surface, the front surface of the stacked chip facing the front surface of the substrate chip; and a top insulating layer stacked on the stacked chip layer furthest from the substrate chip layer. A vertical interconnection hole for vertically connecting the corresponding pins is formed inside the inter-chip insulating layer, and the corresponding pins refer to specified pins that need to be electrically connected; a conductive material layer for electrically connecting the corresponding pins is formed in the vertical interconnection hole; and the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

WANG YAO (CN)
LING YUNZHI (CN)
CUI YINHUA (CN)
HU CHUAN (CN)
LI ZIBAI (CN)
ZHAO WEI (CN)
CHEN ZHITAO (CN)

PCT/CN2021/111018

February 09, 2023

August 05, 2021

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INST OF SEMICONDUCTORS GUANGDONG ACADEMY OF SCIENCES (CN)

H01L23/498; H01L21/60

CN110993518A	2020-04-10
US7901989B2	2011-03-08
CN101465343A	2009-06-24
CN104051337A	2014-09-17
CN105529276A	2016-04-27

CHOFN INTELLECTUAL PROPERTY (CN)

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