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Title:
A CHIP STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2019/151960
Kind Code:
A1
Abstract:
In the present invention, a chip structure, suitable to be used in radar applications is provided. Said chip structure comprises, at least one gallium based first layer (1) to perform RF applications; at least one gallium based second layer (2), placed on said first layer (1), to perform digital applications; at least two copper based pillars (3) located between the first layer (1) and the second layer (2), which provide electrical connection between the first layer (1) and second layer (2) and which ensure that there is a safe distance between the first layer (1) and second layer (2).

Inventors:
AKTUĞ, Ahmet (Mehmet Akif Ersoy Mahallesi 296 Cadde No:16, Yenimahalle/Ankara, 06370, TR)
DAĞDELEN, Murat Erdal (Mehmet Akif Ersoy Mahallesi 296 Cadde No:16, Yenimahalle/Ankara, 06370, TR)
Application Number:
TR2018/050032
Publication Date:
August 08, 2019
Filing Date:
January 30, 2018
Export Citation:
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Assignee:
ASELSAN ELEKTRONİK SANAYİ VE TİCARET ANONİM ŞİRKETİ (Mehmet Akif Ersoy Mahallesi 296 Cadde No:16, Yenimahalle/Ankara, 06370, TR)
International Classes:
H01Q21/00; H01Q3/26; H01Q21/06; H01Q23/00
Foreign References:
US5262794A1993-11-16
US20090184864A12009-07-23
US7508267B12009-03-24
US6002375A1999-12-14
Attorney, Agent or Firm:
DESTEK PATENT, INC. (Lefkoşe Cad. NM Ofis Park B Blok No:36/5, Beşevler, Nilüfer/Bursa, 16110, TR)
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Claims:
CLAIMS

1. A chip structure, suitable to be used in radar applications, characterized by comprising;

- at least one gallium based first layer (1 ) to perform RF applications;

- at least one gallium based second layer (2), placed on said first layer (1 ), to perform digital applications;

- at least two copper based pillars (3) located between the first layer (1 ) and the second layer (2), which provide electrical connection between the first layer (1 ) and second layer (2) and which ensure that there is a safe distance between the first layer (1 ) and second layer (2).

2. A chip structure according to claim 1 , characterized in that; length of said pillars (3) is between 30-50 urn.

3. A chip structure according to claim 1 , characterized in that; length of said pillars (3) is 40 urn.

4. A power amplifier system according to claim 1 , characterized in that; components of the second layer (2) face the first layer (1 ).

5. A power amplifier system according to claim 1 , characterized in that; first layer (1 ) is in the form of a four channelled chip.

6. A power amplifier system according to claim 1 or 5, characterized in that; second layer (2) is in the form of a four channelled chip.

Description:
A CHIP STRUCTURE

Field of the Invention

The present invention is related to a chip structure especially suitable to be used in phased array radar applications.

Background of the Invention

Phased array radars consists of multiple receive and / or transmit modules and antennas which have to be separated by certain distance imposed by wavelength. Depending on frequency band of operation, distance between modules has to be very small. In phased array radar applications, different tasks (such as sending signals, receiving signals, processing signals etc.) are performed almost simultaneously. Due to both limited available space for each microwave module and high number of task assigned, chips used in modules are required to be small in size. Moreover, brittle nature of chips brings maximum chip size limitations for handling.

Most of the silicone based semiconductor technologies are compliant with analogue, digital, and RF circuits, therefore it is possible to form a silicone based compact multi channel chip having analogue, digital, and RF circuits simultaneously. However, some critical RF performance of the silicon based technologies are limited (noise figure, output power etc.) compared other semiconductor technologies (such as gallium arsenide). Although, GaAs based technologies have better RF performance, it has lower level of integrity than silicone based technologies which increases the chip dimensions to unacceptable levels.

Brief Description of the Invention

In the present invention, a chip structure, suitable to be used in phased array radar applications is provided. Said chip structure comprises, at least one gallium based first layer to perform RF applications; at least one gallium based second layer, placed on said first layer, to perform digital applications; at least two copper based pillars located between the first layer and the second layer, which provide electrical connection between the first layer and second layer and which ensure that there is a safe distance between the first layer and second layer to prevent any undesired RF couplings.

In the present application, the chip structure has plurality of layers for performing different applications (namely RF applications and digital applications). RF applications are performed with high performance in first layer and digital applications are performed in second layer. Therefore, with the chip structure of the present application, both RF applications and digital applications are performed in a much smaller footprint.

Object of the Invention

An object of the invention is to provide a chip structure performing both digital and RF applications.

The other object of the invention is to provide a compact chip structure having high performance on digital and RF applications.

Another object of the invention is to provide a chip structure suitable to be used in phased array radar applications.

Brief of the Drawings

Figure 1 ; is perspective view of the chip structure of the present application.

All the parts illustrated in the drawing are individually assigned a reference numeral and the corresponding terms of these numbers are listed as follows:

First layer (1 )

Second layer (2)

Pillar (3)

Detailed Description of the Invention

In the radar applications, digital and RF circuits are needed to be used together. In order to perform multi-channel digital and RF processes on a single chip, silicone based structures are commonly used. However, since RF performance of the silicone based structures are limited, overall performances of said single chip structures are limited. Therefore, with the present invention, a chip structure performing both digital and RF applications is provided.

A perspective view of the chip structure of the present invention is given in figure 1 . Said chip structure comprises at least one gallium based (such as gallium arsenide - GaAs, gallium nitride - GaN etc.) first layer (1 ) to perform RF applications; at least one gallium based (such as gallium arsenide - GaAs, gallium nitride - GaN etc.) second layer (2), placed on said first layer (1 ), to perform digital applications; at least two copper based pillars (3) located between the first layer (1 ) and the second layer (2), which provide electrical connection between the first layer (1 ) and second layer (2) and which ensure that there is a safe distance between the first layer (1 ) and second layer (2).

In an exemplary embodiment of the present invention, gallium arsenide based first layer (1 ) is connected to a control unit for sending/receiving signals/commands. Signals/commands received by the first layer (1 ) are sent to the second layer (2) through copper based pillars (3). Therefore, a safe electrical connection between the first layer (1 ) and second layer (2) is provided. Moreover, said pillars (3) ensure that there is a safe distance between the first layer (1 ) and second layer (2). In detail, during the design of the first layer (1 ), it is assumed that there is only air above the first layer (1 ). Therefore, in order to perform desired RF functions, parameters of the first layer (1 ) determined accordingly. Flowever, when a second layer (2) is placed on top of the first layer (1 ), RF functions of the first layer (1 ) may be effected. In order to avoid such situation, there must be a safe distance between the first layer (1 ) and second layer (2). Since said pillars (3) ensures said safe distance, according to the present invention, RF performance of the first layer (1 ) is not effected by the second layer (2).

In a preferred embodiment of the present application, length of each said pillars (3) is between 30-50 urn (preferably 40 urn). Studies show that, when the distance between the first layer (1 ) and second layer (2) is kept higher than 50 urn, RF performance of first layer (1 ) is minimally affected by second layer (2).

In another preferred embodiment of the present application, components of the second layer (2) face the first layer (1 ). Thanks to said structure, connection between the first layer (1 ) and second layer (2) is provided more easily and reliably. In another preferred embodiment of the present application, first layer (1 ) is in the form of a four channelled chip. Similarly, second layer (2) is preferably in the form of a four channelled chip. Therefore, in this embodiment, chip structure has four channels. Thanks to the multilayer structure of the chip structure of the present application, four channel chip is provided with small size.

In the present application, the chip structure has plurality of layers for performing different applications (namely RF applications and digital applications). RF applications are performed with high performance in first layer (1 ) and digital applications are performed in second layer (2). Therefore, with the chip structure of the present application, both RF applications and digital applications are performed in a much smaller footprint.