Title:
CHIP AND VOLTAGE NOISE SUPPRESSION METHOD
Document Type and Number:
WIPO Patent Application WO/2023/202305
Kind Code:
A1
Abstract:
Disclosed in the present application are a chip and a voltage noise suppression method, belonging to the technical field of power management. The chip comprises a plurality of processors located in the same power domain, and a power consumption monitoring module and a power consumption regulation module, the power consumption monitoring module being used for acquiring power consumption change information of the plurality of processors, and for transmitting the power consumption change information to the power consumption regulation module, and the power consumption regulation module being used for performing, according to the power consumption change information of the plurality of processors, power consumption suppression on some or all of the plurality of processors. In the present application, for a scenario in which a plurality of processors share a power supply, power consumption suppression is performed by comprehensively considering the power consumption change information of the plurality of processors, thereby achieving more accurate and timely power consumption suppression on the processors, effectively suppressing voltage noise, and reducing performance damage to the processors.
Inventors:
CHENG WANJUAN (CN)
LIU YU (CN)
LIU ZHEN (CN)
LIU KAI (CN)
LIU YU (CN)
LIU ZHEN (CN)
LIU KAI (CN)
Application Number:
PCT/CN2023/082803
Publication Date:
October 26, 2023
Filing Date:
March 21, 2023
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F1/3206
Domestic Patent References:
| WO2021114155A1 | 2021-06-17 | |||
| WO2021232266A1 | 2021-11-25 |
Foreign References:
| CN113886196A | 2022-01-04 | |||
| US20150082060A1 | 2015-03-19 | |||
| CN113641550A | 2021-11-12 |
Attorney, Agent or Firm:
TDIP & PARTNERS (CN)
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