FIELD OF THE INVENTION The invention relates to a chip, which chip has a substrate and an integrated circuit having a plurality of active circuit components that is provided on the substrate, and which chip has a passivating layer, and which chip has, between the integrated circuit and the passivating layer, a plurality of layer-like line zones, in which line zones useful lines are provided and between which line zones layer- like isolating zones are provided to isolate the line zones and the useful lines contained therein from one another electrically, which useful lines are intended to connect active circuit components of the integrated circuit and to pass on useful signals and which isolating zones are provided with through-holes, in which through- holes are provided vias by means of which two useful lines situated in immediately adjoining line zones are connected together by an electrically conductive connection.

BACKGROUND OF THE INVENTION A chip of the design set out in the first paragraph above has been marketed in many variant versions and is therefore known. In many cases, there exists with the known chip the problem that, at greater or lesser cost in terms of time, money and effort, at least one of its many functions can be reverse engineered, or in other words spied out, in an undesirable way, because access to the various useful lines is possible in successive steps by applying etching processes that follow one another in an intelligent sequence, thus enabling at least one function of the known chip to be determined with the help of a large number of probe steps. Any such unwanted determining of at least one of its functions is extremely problematic, particularly when secret data is stored in the chip. A field of application where the unwanted determining of a function of a chip is especially critical is that of data carriers suitable for and arranged for contactless communication, such as, for example. Chip cards or vehicle immobilizers, because in these areas of application particularly unpleasant and severe disadvantages can arise for the user concerned if unauthorized persons succeed in reverse engineering an important function of the chip. It should be mentioned that there have already been studies of and solutions for the provision of protection against any unwanted spying-out of a function of a chip. In this connection, attention may for example be drawn to US patent document US 5,861,662 A. There is known from this patent document a solution in which the chip is accommodated in a chip package, there being provided, inside the chip package and outside the chip and to provide protection against a function of the chip being spied out in an unwanted way, a plurality of connecting bond wires or lines that together form a line configuration that is spread out in a planar form, the spacing between the individual connecting bond wires being selected to be so small that it becomes very difficult for probe needles to be passed through between the connecting bond wires, which is beneficial from the point of view of providing protection against a function of the chip contained in the chip package being spied out in an unwanted way. However in the known design, the spacing between the connecting bond wires provided as a means of protection is relatively large in relation to the probe needles currently obtainable, which means that it is relatively easy with probe needles such as are now available to get through between the connecting bond wires to the useful lines situated below the passivating layer. Also connecting bond wires of this kind can be cleared out of the way by shifting them mechanically, thus enabling larger spacings to be obtained between the connecting bond wires, which makes access for probe needles easier. There is also the problem with the known solution that the connecting bond wires provided in the chip package can, with relative ease, be removed and replaced by other bypassing lines, which is likewise undesirable with a view to having protection that is as good as possible against any unwanted spying out of a function of a chip. It should also be mentioned that the production of connecting bond wires of this kind means additional costs, which has a disadvantageous effect on the cost of producing a chip package containing a chip worth protecting.

OBJECT AND SUMMARY OF THE INVENTION It is an object of the invention to remedy the less beneficial circumstances described above and to produce an improved chip, easily and by using simple means. To achieve the object described above, features according to the invention are provided in a chip according to the invention, thus enabling a chip according to the invention to be characterized in the manner specified below, namely: A chip, which chip has a substrate and an integrated circuit, having a plurality of active circuit components, that is provided on the substrate, and which chip has a passivating layer, and which chip has a plurality of layer- like line zones between the integrated circuit and the passivating layer, in which line zones useful lines are provided and between which line zones layer-like isolating zones are provided to isolate the line zones and the useful lines contained therein from one another electrically, which useful lines are intended to connect active circuit components of the integrated circuit and to pass on useful signals and which isolating zones are provided with through-holes, in which through-holes are provided vias by means of which two useful lines situated in immediately adjoining line zones are connected together by an electrically conductive connection, wherein the chip is provided in its interior with protective means for protection against any unwanted spying-out of a function of the chip, wherein dummy lines are provided as protective means in at least one line zone of the chip, and wherein there are no electrically conductive connections between the dummy lines and the active circuit components and, consequently, no useful signals occur on the dummy lines when the chip is operating. By the provision of the features according to the invention, there is obtained, easily and at no major additional expense or effort, a chip that is provided in its interior with protective means for protection against any unwanted spying-out of at least one function of the chip, which gives the advantage that, in the case of the solution according to the invention and in contrast to what is possible in the case of the solution described above, it is not possible for the protective action of the protective means to be altered outside the chip, which is advantageous with a view to obtaining protection that is as great as possible. A further advantage of the provisions according to the invention is that the production of the protective means requires virtually no additional effort or expenditure, because the production of the dummy lines that are provided as protective means is possible, and is performed, simultaneously with the production of useful lines that are present anyway, which means that the production of the dummy lines merely imposes additional costs for material but no additional procedural costs, which is advantageous with a view to producing a chip as inexpensively as possible. Also, the making of the provisions according to the invention ensures a considerably higher level of protection than in the case of the known solution because dummy lines provided in accordance with the invention can be produced to particularly small widths and at particularly small spacings - as is already known for useful lines - thus making it virtually impossible for probe needles to be passed through between two useful lines or dummy lines. Nor other bypass lines can replace dummy lines provided in accordance with the invention. To sum up, it can therefore be said that, with the help of the protective means that are provided inside the chip and that are implemented in the form of dummy lines, a particularly high level of protective action is ensured against any unwanted spying out of at least one function of a chip. In a chip according to the invention it has proved very advantageous if the dummy lines are provided in addition to the useful lines in at least one line zone. An arrangement of this kind has proved advantageous with a view to providing protection against any spying out of at least one function of chip because this arrangement calls for only very little effort and expenditure for its implementation. In a chip according to the invention it has also proved very advantageous if, apart from chip-connecting contacts (pads) and any useful lines leading to the chip- connecting contacts that may, if required, be present in the line zone in question, only dummy lines are provided in the line zone immediately adjacent the passivating layer. An arrangement of this kind has proved particularly advantageous because there is then already a strong barrier against any unwanted spying out of at least one function of a chip according to the invention in a region of a chip of this kind that is situated very far towards the exterior. In a chip according to the invention it has proved very advantageous if at least some of the dummy lines provided in a line zone each have an electrically conductive connection to at least one via, which at least one via extends from the line zone to the line zone that is adjacent to it and that is situated nearer to the integrated circuit. What is achieved in this way is that the presence of useful vias can be simulated, which makes a major contribution to making it considerably more difficult for at least one function of a chip according to the invention to be spied out. In a chip according to the invention as described in the previous paragraph, it has also proved very advantageous if the at least one via has an electrically conductive connection to a dummy line in the adjacent line zone situated nearer to the integrated circuit and consequently dummy lines are provided in at least two line zones. What is obtained in this way is a further obstacle to any unwanted spying out of at least one function of a chip according to the invention, because, in a spying-out operation, at least two line zones have to be spied out and overcome. In a chip according to the invention as described above, it has proved particularly advantageous if dummy lines are provided in all the line zones that are present. The great advantage that this gives is a particularly high level of protection against any unwanted spying out of at least one function of a chip according to the invention, because all the line zones present have to be examined and overcome which, with the chips having five to nine line zones that are usual at the moment, will entail the expenditure of an enormous amount of time, money and effort. In a chip according to the invention as described in the previous paragraph, it has proved advantageous if the dummy lines and the useful lines are of the same width. The reason why this is very advantageous is because it makes it very difficult to distinguish between useful lines and dummy lines. It is also useful if the spacings between the useful lines and the dummy lines are of equal widths, and are preferably of a width equal to the equal widths of the useful lines and dummy lines. In a chip according to the invention it has also proved very advantageous if some of the dummy lines are at a given potential when the chip is operating. An arrangement of this kind is particularly advantageous because the application of a given potential to dummy lines provides particularly effective assistance with the pretence that dummy lines are useful lines. The application of a given potential to dummy lines is also useful against crosswalk to said dummy lines. It is very advantageous in this case if what is selected as the given potential is the ground potential. It has also proved very advantageous if, in addition to the active circuit components, stock circuit components are also included in the integrated circuit and if at least some of the stock circuit components are connected to at least one dummy line and, when the chip is operating, are at at least one given potential. This provision makes any unwanted spying out of at least one function of a chip according to the invention particularly difficult because the occurrence of a given potential at a given number of stock circuit components simulates the use of these stock circuit components as active circuit components, which they are not in fact. It has long been known for various gates, transistors, capacitors, resistors or sensors to be provided as stock circuit components of this kind. Such stock circuit components are often referred to by those skilled in the art as "X-boxes". These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter, to which however the invention is not limited.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Fig. 1 is a schematic cross-section showing part of a known prior-art chip. Fig. 2 is a view from above of a chip according to a first embodiment of the invention, which chip has five line zones arranged one above the other that are shown in Fig. 2. Fig. 3 is a cross-section through part of the chip shown in Fig. 2, taken on the thick line shown in Fig. 2. Fig. 4 is a view similar to Fig. 2, showing the chip of Figs. 2 and 3 but showing only the topmost, fifth line zone and the fourth line zone situated below it and showing, in these zones, all the useful lines and some of the dummy lines. Fig. 5 is a view similar to Fig. 2, showing the chip of Figs. 2, 3 and 4 but showing only the topmost, fifth line zone and the fourth line zone situated below it and showing, in these zones, only all the useful lines. Fig. 6 is a view similar to Figs. 2 and 4, showing a chip according to a second embodiment of the invention but showing only one line zone and showing, in this line zone, both all of the useful lines and all of the dummy lines. Fig. 7 is a view similar to Figs. 2, 4, 5 and 6 showing the chip of Fig. 6 but showing one line zone and showing, in this line zone, only all the useful lines.

DESCRIPTION OF EMBODIMENTS Fig. 1 shows part of a known prior-art chip 1, which chip 1 is produced on the basis of silicon. It should be mentioned that such a chip might also be produced on the basis of a polymer material. The chip 1 has a substrate 2 that may also be referred to as a base member. Produced on the substrate 2 is an integrated circuit 3 that is only indicated very schematically in Fig. 1. The production and configuring of an integrated circuit 3 of this kind is generally familiar to those skilled in the art and therefore does not need to be described in any greater detail in the present connection. The integrated circuit 3 contains a plurality of circuit components 4 and, in addition to the active circuit components 4, stock or "X-box" circuit components 5. The active circuit components 4 are provided in the integrated circuit 3 in such a way that they are active when the integrated circuit 3 is operating and are used to perform the various functions of the integrated circuit 3. The stock circuit components 5 were originally provided only for stock purposes and are used, if required, as active circuit components. This measure has long been known to those skilled in the art and for this reason there is no need for it to be considered in any greater detail here. On its face region remote from the substrate 2, the chip 1 is provided with a passivating layer 6. The passivating layer 6 is often also referred to as a protective layer or covering layer. The passivating layer 6 is intended and arranged to protect the parts of the chip 1 that are situated beneath it. The passivating layer 6 is preferably composed of silicon nitride (SiN) but may also be produced from other materials. Provided in the passivating layer 6 are through-holes 7, through which through-holes 7 electrically conductive chip contacts (pads) PADl, PAD2, PAD3 and PAD4 are accessible, which is likewise something that is generally familiar. Between the integrated circuit 3 and the passivating layer 6, the chip 1 has a total of five layer-like lines zones MEl, ME2, ME3, ME4 and ME5. To isolate the line zone MEl from the integrated circuit 3 electrically, and to isolate the line zones MEl to ME5 from one another electrically, layer-like isolating zones ISl, IS2, IS3, IS4 and IS5 are provided. Isolating zones ISl, IS2, IS3, IS4 and IS5 are composed of an isolating layer of non- conductive oxide, which is also intended for planarizing purposes. Provided in the line zones MEl to ME5 are useful lines Ll, L2, L3, L4, L5, L6, L7, L8, L9, LlO, LIl, L12, L13, L14, L15, L16 and L17. The above-mentioned pads are formed by means of the useful lines Ll 4, L15, L16 and L17 situated in the topmost, fifth line zone ME5. The useful lines in each line zone MEl to ME5 preferably extend in one direction and parallel to one another. The useful lines in two mutually adjacent line zones preferably extend perpendicularly to one another in this case. The useful lines are isolated from one another by means of the isolating zones ISl to IS5. The useful lines are intended for connecting the active components 4 of the integrated circuit 3 and for passing on useful signals. To make it possible for these functions to be performed, some of the useful lines in different line zones MEl to ME5 are connected together electrically, where this is required. For this purpose, the isolating zones ISl to IS5 are provided with through- holes but these have not been given reference numerals in Fig. 1 so that the clarity of the drawing will not be reduced unnecessarily. Provided in the through-holes in the isolating zones ISl to IS5 are through-lines that are often referred to by those skilled in the art as "vias". In Fig. 1, only some of the vias shown have been identified by the reference TL. With the help of the vias TL, two useful lines that are situated in immediately adjoining line zones MEl to ME5 are connected together by an electrical conductive connection. The useful lines Ll to L17 and the vias TL are produced by known methods, something that has long been known and will therefore not be described in detail here. It should be mentioned that the useful lines and the vias are produced with the help of aluminum. These items may however also be produced from other metals or metal alloys. In the case of a chip 1 as has been described above by reference to Fig. 1 and that is of a known prior-art design, is has been found that there is a great demand for protection against any unwanted spying out of at least one function of the chip 1. Spying out of this kind can be performed by etching away, in successive steps, zones lying one above the other, or by etching away, in successive steps, small parts of successive zones, measurements being made, after each etching operation has been performed, at what is termed a tip measuring point by means of so-called probe needles, a process which is referred to by those skilled in the art as "probing". To meet the above-mentioned demand, in a first embodiment of the invention, the design of the chip 1 shown in Fig. 2 is made such that the chip 1 is provided in its interior with protective means 10, which protective means 10 are intended and arranged to provide protection against any unwanted spying out of at least one of the many functions of the chip. The protective means 10 are implemented in this case by means of dummy lines, of which dummy lines only some of those actually present are identified in Figs. 2, 3 and 4 by the references DLl, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DLlO, DLl 1, DL12 and DLl 3. Only some of the dummy lines actually provided are shown in Figs. 2 and 4, so that there are no additional obstacles to the intelligibility of these Figures, and particularly that of Fig. 2. In the chip 1 that is actually produced, the dummy lines are so tightly packed that virtually the entire area of a line zone is filled with lines, so that what exists is a grille structure covering virtually the whole area. There are no electrically conductive connections between the dummy lines, i.e. between dummy lines DLl to DL13 for example, and the active circuit components 4, and consequently no useful signals occur on the dummy lines when the chip 1 is operating. In the case of the chip 1 shown in Figs. 2 to 5, the dummy lines according to the invention are provided in all five of the line zones MEl to ME5. In this connection, attention is directed in particular to Figs. 4 and 5, because it can clearly be seen from these Figures how the two line zones ME4 and ME5 differ from one another with regard to dummy lines being provided and not being provided. In Fig. 4, both the useful lines and also some of the dummy lines in the fourth line zone ME4 and the fifth line zone ME5 are shown, whereas in Fig. 5 it is only the useful lines in the fourth line zone and the fifth line zone that are shown. Of the useful lines shown in the fifth line zone ME5, three are identified by reference numerals, namely by reference numerals L20, L21 and L22. Of the useful lines situated in the fourth line zone ME4 situated below the fifth line zone ME5, three are likewise identified by reference numerals, namely by reference numerals L23, L24 and L25. It should be mentioned that it is not essential for dummy lines to be provided in all five of the line zones Ml to ME5. It should also be mentioned that in a chip forming a modified version of the chip 1 shown in Figs. 2 to 5 it has proved particularly advantageous if what are provided in the line zone immediately adjacent to the passivating layer 6, i.e. in the topmost, fifth line zone ME5, are, apart from the pads required in said line zone ME5 and the useful lines leading to these pads, only dummy lines. However, when required, no useful lines leading to the pads need to be provided in the topmost, fifth line zone ME5, namely when the connections to the pads are made by means of vias TL passing through the fifth isolating zone IS5. As can be seen from Figs. 3 and 4, the dummy lines DLl and DL2 provided in the topmost, fifth line zone ME5 each have an electrically conductive connection to at least one via, with dummy line DLl having an electrically conductive connection to two vias TLl and TL2 and the second dummy line DL2 having an electrically conductive connection to one via TL3. The three vias TLl, TL2 and TL3 extend from the fifth line zone ME5 to the fourth line zone ME4 that is situated adjacent the latter and closer to the integrated circuit 3, with via TLl having an electrically conductive connection to the dummy line DL3 situated in the fourth line zone ME4, via TL2 having an electrically conductive connection to the dummy line DL6 situated in the fourth line zone ME4, and via TL3 having an electrically conductive connection to the dummy line DL7 situated in the fourth line zone ME4. The arrangement that is described in detail above, which comprises dummy lines DLl and D12, vias TLl, TL2 and T13 and dummy lines DL3, DL6 and DL7, is produced in an entirely similar way in many other regions of the chip 1. This produces a line configuration comprising a plurality of useful lines, dummy lines and vias, which line configuration is of such a complicated and confusing construction that any reverse engineering or spying out of at least one function of the chip 1 is made more difficult, or prevented, to such a high degree that it is virtually impossible for any such spying out to be performed successfully. This is because spying out of this kind is only possible by removing, i.e. ablating and in particular etching away, lines, in which case however, when such a process of removing lines is performed, the problem repeatedly arises for the person doing the spying out that a line is removed but after its removal it is no longer possible for the chip 1 to operate, thus frustrating any spying out. Removal, and in particular etching away, of dummy lines may also result in such pronounced changes in the capacitive couplings between the lines (useful lines and dummy lines) that there are marked changes in signal propagation times, after which the chip 1 is no longer able to operate, so that in this way too any spying out is frustrated. With regard to what is termed the wiring of the chip 1, it should also be mentioned that, for passing on signals when the chip 1 is operating, useful lines that extend in line zones lying at deeper levels are selected for signals that are of great importance and consequently have a great need for security. It should also be mentioned that in ordinary chips the wiring density per line zone is often a maximum of 50 %. Because of the additional provision of the dummy lines, it becomes possible in a chip according to the invention for a wiring density of up to close to 100 % to be obtained in each line zone MEl to ME5. This makes possible or ensures a particularly high level of protection against any unwanted spying out. It should also be mentioned that in chips that can be produced at the moment having a plurality of line zones (wiring levels), having for example five to nine line zones, the planarization of the line zones and the isolating zones is already so good that if a line zone is looked at (in plan) under a microscope, the vias situated below useful lines and dummy lines are undetectable because they are so well covered by the useful lines and dummy lines. What this means is that only after the line zone, i.e. the useful lines and dummy lines provided therein, has been removed is it possible to detect whether there are one or more vias running through to the next line zone situated below. This makes a particularly high level of protection possible against any unwanted spying out. As can be seen from Figs. 4 and 5 in particular, in the case of line zones ME5 and ME4 the dummy lines and the useful lines are of the same width. The same relative widths also exist in the other line zones, ME3, ME2 and MEl. This arrangement is advantageous with a view to affording the least possible opportunity for distinguishing the useful line and dummy lines from one another. Shown in Figs. 6 and 7 is part of a further chip 1 according to the invention, only the seventh line zone ME7 being shown in detail. It can clearly be seen from these two Figures how the arrangements in this seventh line zone ME7 differ from one another in respect of dummy lines being, or not being, provided. In Fig. 6 are shown both the useful lines and the dummy lines in the seventh line zone ME7, whereas in Fig. 7 is it only the useful lines in the seventh line zone that are shown. In a chip according to the invention that is not shown in the drawings, a voltage source is provided that is separated in an especially secure manner from the other active circuit components of the integrated circuit 3 and that makes available a given potential. In this chip, some of the dummy lines are at the given potential at least when the chip is operating, in which case the said voltage source is then activated. In another version of this chip, all the dummy lines are at the given potential. Due to the fact that some or all of the dummy lines are at the given potential, the advantage is obtained that a greater pretence can be made that dummy lines are useful lines. What is also obtained in this way is the advantage that, as a result of the application of a given potential to at least some of the dummy lines, there is better protection against cross-talk to the dummy lines, as has been shown in tests. Rather than a voltage source, a current source may also be provided. In a further chip according to the invention, which is not shown in the drawings, an arrangement is provided in which at least some stock or "X-box" circuit components (see the stock circuit components 5 of the known chip 1 shown in Fig. 1) are connected to at least one dummy line of the chip, in which case, at least when the chip in question is operating in such a way that a voltage source is activated to emit a given potential, the given potential emitted by the voltage source is applied to the at least one dummy line and consequently to the proportion of the stock circuit components that are connected to the dummy lines. This simulates active use being made of stock circuit components, which is likewise advantageous with a view to making it difficult or impossible for at least one function of the chip to be spied out.