METHOD OF FORMING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of Singapore application No. 10201602751U filed on April 7, 2016, the contents of it being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[0002] Various aspects of this disclosure relate to circuit arrangements, memory columns, memory arrays, and/or methods of forming the same.

BACKGROUND

[0003] A typical magnetic random access memory (MRAM) includes an array of magnetoresistive memory elements. Each magnetoresistive memory element, such as a magnetic tunnel junction (MTJ), typically has a structure that includes multiple magnetic layers separated by various non-magnetic layers. Information is stored as magnetic states due to different magnetization directions of the magnetic layers. The magnetization directions may be represented by magnetization vectors, and the structure exhibits a varying electrical resistance based on the magnetic state.

[0004] The magnetization direction in one magnetic layer is usually magnetically fixed or pinned (the magnetic layer may be referred to as a fixed layer), while the magnetization direction of another magnetic layer may be free to switch between the same and opposite directions as that of the fixed layer. This other layer may be referred to as a free layer.

[0005] When the magnetic vector of the free layer is parallel or anti-parallel to that of the fixed layer, the structure is in respectively in the "parallel" state and "antiparallel" state. The memory element is in a low (logic "0" state) electrical resistance state when the structure is in the parallel magnetic state, and a high (logic "1" state) electrical resistance state when the structure is in an antiparallel magnetic state. The low-resistance value may be denoted as Rp (i.e. parallel resistance) and the high-resistance value may be denoted as RAP (i.e. anti-parallel resistance). [0006] A sensing circuit may be used to detect or determine the electrical resistance of the structure to obtain information stored in the magnetic memory element. Typically, a high magnetoresistance (MR) value, which is the ratio of the resistance difference of the two states to the resistance of the low resistance state, i.e. (MR = (RA _P -Rp) / Rp), is desirable for increasing speed of signal sensing and fast read operation.

[0007] There are two different methods used to program the free layer: field switching and spin-torque-transfer switching (STT). In STT MRAM, switching is carried out using current pulse through the MTJ. The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer, with the final state (parallel or antiparallel) determined by the polarity of the current pulse. The current is passed from the free layer to the fixed layer in order to write a "0" to the cell (i.e. final resistance value is Rp, i.e. low, and the cell is in the low resistance state). The current direction is passed from the fixed layer to the free layer in order to write a "1" to a cell (i.e. final resistance value is RAP, i.e. high, and the cell is in the high resistance state). Usually the fixed layer sits right on top of the bottom electrode (BE) while the free layer is right below the top electrode (TE).

[0008] The most popular and densest STT-MRAM cell is the 1T1M (one transistor one MTJ) design. FIG. 1 shows a 1T1M bit cell 100. The cell 100 includes one MTJ 102 and one transistor 104 connected in series. Usually, the BE of the MTJ 102 is connected to the drain terminal of the access transistor 104 while the TE of the MTJ 102 is connected the bit line (BL), which may be shared among all cells in the same column. The source of the access transistor 104 is also connected to the source (SL), which may also be shared among all cells in the same column.

[0009] The word line (WL) runs in a horizontal direction and may be shared between the cells on the same row. To program a particular cell, the WL is pulsed to VDD, while the BL and SL are conditioned according to the desired input value. For example, in order to write a "1", SL may be pulled to high voltage VH, while BL may be pulled to low voltage VL SO that the current flows from BE thought the fixed layer to the free layer, then to the TE. In order to write a "0", BL may be pulled to high voltage VH, while SL may be pulled to low voltage VL so that the current flows from TE thought the free layer to the fixed layer, then to the BE. VH is usually close to or about VDD, while VL is usually close to or about ground. [0010] Since ST-MRAM switching current requirements reduce with decreasing dimensions of magnetic tunneling junction (MTJ), STT-MRAM has the potential to scale at even the most advanced technology nodes.

[0011] However, increasing variability in the MTJ resistance makes sensing difficult, thus negatively impacting the read speed. A differential bit-cell including 2 transistors and 2 MTJs (i.e. 2T2M cell) has been proposed to address this issue as the differential bit-cell provides a greater read noise margin. FIG. 2A shows a 2T2M bit cell 200. The cell 200 includes 2 MTJs 202a, 202b, and 2 transistors 204a, 204b.

[0012] Correspondingly, each column has two bit lines (BL and BLB) and two source lines (SL and SLB). For example to write a "1", SL may be pulled to high voltage VR while BL may be pulled to a low voltage VL to write RAP in the first MTJ 202a, and at the same time, BLB may be pulled to high voltage VR while SLB is pulled to low voltage VL to write R _P in the second MTJ. The cell 200 may involve more dynamic switching power of the signal lines as well as a more complex control circuit. FIG. 2B shows a plot 250 of the write operation of the cell 200 shown in FIG. 2A. 4 signals are required to write to 2 MTJs. The magnitude of the signals is plotted as a function of time.

[0013] At the array level, circuitry for sense amplifiers provides proper functionality and performance of the memory during read operation. Conventional sensing design biases the clamping devices (using a V _c i _amp so that the BL voltage swing is reduced to minimize disturbances to the MTJ during the read operation. It also forces the sources of the clamping devices to VBL ⁼ VBLB = _c i _am p - Vth, where V _t h is the threshold voltage of n-channel metal oxide semiconductor (NMOS) transistor, VBL is the voltage at BL, and VBLB is the voltage at BLB. As a result, the currents flowing through BL and BLB (denoted by ¾L and ¾LB respectively) are determined by Vdamp - V _t h and the combined resistance of the MTJ and the access transistor. By sensing the current difference between ¾L and IBLB, data stored in the MTJ can be determined.

[0014] This approach has major disadvantages because VBL is always different from VBLB due to the imperfection of the fabrication process as well as the circuit topology. For example, to ensure that VBL = VBLB, the clamp devices must be in deep saturation and the two branches must be balanced. Therefore, the differential signal obtained from this approach is limited. SUMMARY

[0015] Various embodiments may provide a circuit arrangement. The circuit arrangement may include a first memory element having a first electrode and a second electrode. The circuit arrangement may also include a second memory element having a first electrode and a second electrode. The circuit arrangement may further include a first access transistor having a control electrode, a first controlled electrode and a second controlled electrode. The circuit arrangement may additionally include a second access transistor having a control electrode, a first controlled electrode and a second controlled electrode. The circuit arrangement may further include a first bit line connected to the first electrode of the first memory element. The circuit arrangement may also include a second bit line connected to the second electrode of the second memory element. The first controlled electrode of the first access transistor may be connected to the second electrode of the first memory element. The first controlled electrode of the second access transistor may be connected to the first electrode of the second memory element. The first access transistor and the second access transistor may be configured so that when the first access transistor is activated via the control electrode of the first access transistor and when the second access transistor is activated via the control electrode of the second access transistor, a first logic state is written to the first memory element when a first current flows from the first memory element to the first bit line, and a second logic state different from the first logic state is written to the second memory element when a second current flows from the second memory element to the second bit line; and the second logic state is written to the first memory element when a third current flows from the first bit line to the first memory element, and the first logic state is written to the second memory element when a fourth current flows from the second bit line to the second memory element.

[0016] Various embodiments may provide a method of forming a circuit arrangement. The method may include providing a first memory element having a first electrode and a second electrode. The method may also include providing a second memory element having a first electrode and a second electrode. The method may further include providing a first access transistor having a control electrode, a first controlled electrode and a second controlled electrode. The method may additionally include providing a second access transistor having a control electrode, a first controlled electrode and a second controlled electrode. The method may also include connecting a first bit line to the first electrode of the first memory element. The method may additionally include connecting a second bit line to the second electrode of the second memory element. The method may further include connecting the first controlled electrode of the first access transistor to the second electrode of the first memory element. The method may additionally include connecting the first controlled electrode of the second access transistor to the first electrode of the second memory element. The first access transistor and the second access transistor may be configured so that when the first access transistor is activated via the control electrode of the first access transistor and when the second access transistor is activated via the control electrode of the second access transistor, a first logic state is written to the first memory element when a first current flows from the first memory element to the first bit line, and a second logic state different from the first logic state is written to the second memory element when a second current flows from the second memory element to the second bit line; and the second logic state is written to the first memory element when a third current flows from the first bit line to the first memory element, and the first logic state is written to the second memory element when a fourth current flows from the second bit line to the second memory element.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which:

FIG. 1 shows a 1T1M bit cell.

FIG. 2A shows a 2T2M bit cell.

FIG. 2B shows a plot of the write operation of the cell shown in FIG. 2A.

FIG. 3 shows a circuit arrangement according to various embodiments.

FIG. 4 shows a schematic of forming a circuit arrangement according to various embodiments.

FIG. 5A shows a circuit arrangement according to various embodiments.

FIG. 5B is a plot showing a writing operation of the circuit arrangement shown in FIG. 5A according to various embodiments.

FIG. 5C is a table summarizing the writing operation of the circuit arrangement shown in FIG. 5A according to various embodiments in comparison to a conventional 2 transistors - 2 magnetic tunneling junctions cell (i.e. 2T2M cell). FIG. 6A shows a circuit column according to various embodiments.

FIG. 6B shows a plot showing a reading operation of the memory column shown in FIG. 6A according to various embodiments.

FIG. 6C shows a plot of voltage (in millivolts or mV) as a function of clamping voltage (in millivolts or mV) comparing the output voltage (V _out ) and cell disturbances measured as voltages across the magnetic tunneling junction (MTJ) in the memory column according to various embodiments.

FIG. 7 A is a schematic of a memory array according to various embodiments.

FIG. 7B is a schematic of the memory column according to various embodiments.

DETAILED DESCRIPTION

[0018] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0019] Embodiments described in the context of one of the methods or circuit arrangements/ memory columns/ memory arrays are analogously valid for the other methods or circuit arrangements/ memory columns/ memory arrays. Similarly, embodiments described in the context of a method are analogously valid for a circuit arrangement/ memory column memory array, and vice versa.

[0020] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0021] The word "over" used with regards to a deposited material formed "over" a side or surface, may be used herein to mean that the deposited material may be formed "directly on", e.g. in direct contact with, the implied side or surface. The word "over" used with regards to a deposited material formed "over" a side or surface, may also be used herein to mean that the deposited material may be formed "indirectly on" the implied side or surface with one or more additional layers being arranged between the implied side or surface and the deposited material. In other words, a first layer "over" a second layer may refer to the first layer directly on the second layer, or that the first layer and the second layer are separated by one or more intervening layers.

[0022] The memory element/ circuit arrangement/ memory column/ memory array as described herein may be operable in various orientations, and thus it should be understood that the terms "top", "bottom", etc., when used in the following description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of the memory element/ circuit arrangement/ memory column/ memory array.

[0023] In the context of various embodiments, the articles "a", "an" and "the" as used with regard to a feature or element include a reference to one or more of the features or elements.

[0024] In the context of various embodiments, the term "about" or "approximately" as applied to a numeric value encompasses the exact value and a reasonable variance.

[0025] As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

[0026] For the sake of clarity and to avoid clutter, not all features in some of the figures have been labelled. Features which are similar to features that have already been labelled may not be labelled to improve clarity and to avoid clutter.

[0027] FIG. 3 shows a circuit arrangement 300 according to various embodiments. The circuit arrangement 300 may include a first memory element 302 having a first electrode (e.g. a top electrode) and a second electrode (e.g. a bottom electrode). The circuit arrangement 300 may also include a second memory element 304 having a first electrode (e.g. a top electrode) and a second electrode (e.g. a bottom electrode). The circuit arrangement 300 may further include a first access transistor 306 having a control electrode, a first controlled electrode and a second controlled electrode. The circuit arrangement 300 may additionally include a second access transistor 308 having a control electrode, a first controlled electrode and a second controlled electrode. The circuit arrangement 300 may further include a first bit line connected to the first electrode (e.g. the top electrode) of the first memory element 302. The circuit arrangement 300 may also include a second bit line connected to the second electrode (e.g. the bottom electrode) of the second memory element 304. The first controlled electrode of the first access transistor 306 may be connected to the second electrode (e.g. the bottom electrode) of the first memory element 302. The first controlled electrode of the second access transistor 308 may be connected to the first electrode (e.g. top electrode) of the second memory element 304. The first access transistor 306 and the second access transistor 308 may be configured so that when the first access transistor 306 is activated via the control electrode of the first access transistor 306 and when the second access transistor 308 is activated via the control electrode of the second access transistor 308, a first logic state is written to the first memory element 302 when a first current flows from the first memory element to the first bit line, and a second logic state different from the first logic state is written to the second memory element 304 when a second current flows from the second memory element to the second bit line; and the second logic state is written to the first memory element 302 when a third current flows from the first bit line to the first memory element 302, and the first logic state is written to the second memory element 304 when a fourth current flows from the second bit line to the second memory element 304.

[0028] In other words, the circuit arrangement 300 may include a first memory element 302, a second memory element 304, a first access transistor 306, and a second access transistor 308. The first memory element 302, the second memory element 304, the first access transistor 306, and the second access transistor 308 may be electrically connected in such a way that the switching on of the transistor 306 and the flowing of a first current in a direction from the transistor 306 through the first memory element 302 to the first bit line may write a first logic state in the first memory element 302, while the switching on of the transistor 308 and the flowing of a second current in a direction from the transistor 308 through the second memory element 304 to the second bit line may write a second logic state. Conversely, the switching on of the transistor 306 and the flowing of a third current in a direction from the first bit line through the first memory element 302 to the transistor 306 may write the second logic state in the first memory element 302, while the switching on of the transistor 308 and the flowing of a fourth current in a direction from the second bit line through the second memory element 304 to the transistor 308 may write the first logic state to the second memory element 304. [0029] Various embodiments may seek to address or mitigate the problems faced by conventional devices or disadvantages of these devices.

[0030] In the current context, "activate" or "switch on" a transistor may refer to putting the transistor in such a state that a substantial current flows between the first controlled electrode and the second controlled electrode. On the other hand, "deactivate" or "switch off may refer to putting the transistor in such a state that no current or an insubstantial current, e.g. a subthreshold current flows between the first controlled electrode and the second controlled electrode.

[0031] In the current context, a first electrical component "connected" to a second electrical component may refer to the first electrical component electrically coupled or electrically connected to the second component. In various embodiments, the first electrical component may be in physical contact with the second electrical component.

[0032] In various embodiments, the first controlled electrode may refer to a drain electrode, while the first controlled electrode may refer to a source electrode. In various other embodiments, the first controlled electrode may refer to a source electrode, while the second controlled electrode may refer to a drain electrode. A control electrode of a transistor may refer to the gate.

[0033] In embodiments, the logic states are written to the first memory element 302 and/or the second memory cell 304 via spin-torque-transfer (STT) switching.

[0034] The first memory element 302 may be a magnetic tunneling junction. The second memory element 304 may be a magnetic tunneling junction. A magnetic tunneling junction, such as the first magnetic tunneling junction or the second magnetic tunneling junction, may also include a first electrode (top electrode), a second electrode (bottom electrode), a free layer in contact with the first electrode (or nearer the first electrode compared to the second electrode), a fixed layer in contact with the second electrode (or nearer the second electrode compared to the first electrode), and a tunneling barrier between the free layer and the fixed layer. The free layer may have a magnetization direction that may be changed in response to an external magnetic field, while the fixed layer may have a fixed magnetization direction. As the first magnetic element or junction 302 and the second magnetic elements or junction 304 are connected within the circuit arrangement 300 in a complementary or opposing manner, with opposite relative arrangements of the fixed layer and the free layer, a first current flowing from the first memory element or junction 302 to the first bit line and a second current flowing from the second memory element or junction 304 to the second bit line may write opposing logic states to the first memory element or junction 302 and the second memory element or junction 304.

[0035] In various embodiments, when the first current flows from the first memory element to the first bit line, the first current may flow from the second electrode of the first memory element through the fixed layer of the first memory element to the free layer of the first memory element, and then to the first electrode of the first memory element. When the second current flows from the second memory element to the second bit line, the second current may flow from the first electrode of the second memory element through the free layer of the second memory element to the fixed layer of the second memory element, and then to the second electrode of the second memory element. As the first current flows from the fixed layer to the free layer in the first memory element, and the second current flows from the free layer to the fixed layer in the second memory element, opposing logic states may be written in the first memory element and the second memory element.

[0036] Likewise, when the third current flows from the first bit line to the first memory element, the third current may flow from the first electrode of the first memory element through the free layer of the first memory element to the fixed layer of the first memory element, and then to the second electrode of the first memory element. When the fourth current flows from the second bit line to the second memory element, the fourth current may flow from the second electrode of the second memory element through the fixed layer of the second memory element to the free layer of the second memory element, and then to the first electrode of the second memory element.

[0037] In various embodiments, a "circuit" may be understood as any kind of a logic implementing entity, which may be special purpose circuitry or a processor executing software stored in a memory, firmware, or any combination thereof. Thus, in various embodiments, a "circuit" may be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g. a microprocessor (e.g. a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor). A "circuit" may also be a processor executing software, e.g. any kind of computer program, e.g. a computer program using a virtual machine code such as e.g. Java. Any other kind of implementation of the respective functions which will be described in more detail below may also be understood as a "circuit" in accordance with an alternative embodiment. [0038] In various embodiments, the circuit arrangement 300 may further include a word line connected to the control electrode of the first access transistor 306 and the control electrode of the second access transistor 308. The first access transistor 306 and the second access transistor 308 may be activated via the word line. The first access transistor 306 and the second access transistor 308 may be activated at the same time via the word line, and may also be deactivated at the same time via the word line.

[0039] In various embodiments, the circuit arrangement 300 may further include a source line connected to the second controlled electrode of the first access transistor 306 and to the second controlled electrode of the second access transistor 308.

[0040] A first common current flowing along the source line may be separated into the first current which flows to the first memory element for writing of the first logic state, and the second current which flows to the second memory element for writing of the second logic state. In various embodiments, the first current may be substantially equal to the second current. In various other embodiments, the first current may not be substantially equal to the second current.

[0041] Further, a second common current along the source line may be formed from the third current flowing from the first memory element, where the second logic state is written, to the source line, and the fourth current flowing from the second memory element, wherein the first logic state is written, to the source line. The third current may be substantially equal to the fourth current. In various other embodiments, the third current may not be substantially equal to the fourth current.

[0042] In various embodiments, the first access transistor 306 and the second access transistor 308 may be of substantially equal size. However, the first transistor 306 and the second transistor 308 being of substantially equal sizes may not result in equal or similar currents flowing in each branch, due to the different resistance values of the MTJs. Even if the access transistors are sized differently to achieve similar currents flowing through each access transistor 306, 308, the currents for writing the first logic state and the second logic state may be different. Having said that, designers may purposely size these access transistors 306, 308 to have different currents follow through the first and second access transistors so that energy efficiency may be optimized. This is because switching between the first logic state and the second logic state may be inherently asymmetrical in MTJ technology. [0043] In various embodiments, the first logic state may be a high resistance state (RAP), and the second logic state may be a low resistance state (Rp). In various alternate embodiments, the first logic state may be a low resistance state (Rp), and the second logic state may be a high resistance state (RRP). Each of the memory element 302, 304 may be configured to switch between the first logic state and the second logic state. The memory element 302 and the memory element 304 may be configured to store opposing or different logic states. When the memory element 302 is in the first logic state, the memory element 304 may be in the second logic state. Conversely, when the memory element 302 is in the second logic state, the memory element 304 may be in the first logic state.

[0044] In various embodiments, the circuit arrangement 300 may be in a first state (e.g. "1" state) when the first memory element 302 is in the first logic state and the second memory element 304 is in the second logic state. Conversely, the circuit arrangement 300 may be in a second state (e.g. a "0" state) when the first memory element 302 is in the second logic state and the second memory element 304 is in the first logic state. In other words, the circuit arrangement 300 may have a bit state that is dependent on the logic state of the first memory element 302 and the logic state of the second memory element 304. The circuit arrangement 300 may be configured to store a single bit. The circuit arrangement may be referred to as a bit-cell, e.g. a STT-MRAM bit-cell.

[0045] The circuit arrangement 300 may also include a sensing circuit to determine whether a state in at least one of the first memory element 302 and the second memory element 304 is the first logic state or the second logic state. In various embodiments, the sensing circuit may be configured to determine the state of the first memory element 302 and the state of the second memory element 304. The sensing circuit may be configured to read or determine the bit stored in the circuit arrangement 300. The sensing circuit may be configured to read or determine the bit stored in the circuit arrangement 300 by determining the state of the first memory element 302 and/or the second memory element 304.

[0046] The sensing circuit may further include a first current source connected to the first bit line. The sensing circuit may also include a second current source connected to the second bit line. The first current source may be configured to provide a first biasing sense current. The second current source may be configured to provide a second biasing sense current substantially equal to the first biasing sense current. The first current source and the second current source may be in a current mirror configuration. [0047] The sensing circuit may further include a two stage amplifier connected to the first bit line and the second bit line. The two stage amplifier may include a first stage configured to generate a first potential based on the first biasing sense current and a second potential based on the second biasing sense current. The first stage may be configured to generate the first potential based on the first biasing sense current and a logic state of the first memory element 302, and may be further configured to generate the second potential based on the second biasing sense current and a logic state of the second memory element 304. The first memory element 302 may have a resistance dependent on the logic state of the first memory cell 302 (i.e. Rp or RAP), and the first potential may be dependent on the resistance and hence the logic state of the first memory cell 302. Similarly, the second memory element 304 may have a resistance dependent on the logic state of the second memory cell 304 (i.e. Rp or RAP), and the second potential may be dependent on the resistance and hence the logic state of the second memory cell 304.

[0048] The first stage may be or may include a common gate amplifier. The common gate amplifier may include a first amplification transistor including a control electrode, a first controlled electrode and a second controlled electrode. The common gate amplifier may also include a second amplification transistor including a control electrode, a first controlled electrode and a second controlled electrode.

[0049] The control electrode of the first amplification transistor may be connected to the control electrode of the second amplification transistor at a common node. The first controlled electrode of the first amplification transistor may be connected to the first current source, and the first controlled electrode of the second amplification transistor may be connected to the second current source. Further, the second controlled electrode of the first amplification transistor may be connected to the first bit line and the second controlled electrode of the second amplification transistor may be connected to the second bit line.

[0050] The common gate amplifier may be configured so that a boost voltage applied to the common node generates the first potential at the first controlled electrode of the first amplification transistor based on the first biasing sense current flowing through the first amplification transistor, and generates the second potential at the first controlled electrode of the second amplification transistor based on the second biasing sense current flowing through the second amplification transistor. [0051] The two stage amplifier may also include a second stage configured to receive a potential difference between the first potential and the second potential.

[0052] The second stage may be a sense amplifier, e.g. a latched based sense amplifier, configured to receive the first potential and the second potential, and generate an output voltage based on the potential difference. The output voltage may indicate a state of the circuit arrangement 300. The second stage may be configured to receive the first potential and the second potential, and may be further configured to determine a logic state of the first memory element 302 and a logic state of the second memory element 304 (i.e. a state of the circuit arrangement 300) based on the first potential and the second potential.

[0053] The two stage amplifier may use current-mode sensing, which may address the issue of limited differential signal faced by the conventional 2T2M cell.

[0054] Various embodiments may provide a memory column. The memory column may include a plurality of memory units. Each memory unit may include a first memory element having a first electrode and a second electrode. Each memory unit may also include a second memory element having a first electrode and a second electrode. Each memory unit may further include a first access transistor having a control electrode, a first controlled electrode and a second controlled electrode. Each memory unit may additionally include a second access transistor having a control electrode, a first controlled electrode and a second controlled electrode. The first controlled electrode of the first access transistor may be connected to the second electrode of the first memory element. The first controlled electrode of the second access transistor may be connected to the first electrode of the second memory element.

[0055] The memory column may further include a first common bit line connected to the first electrode of the first memory element of each unit. The memory column may also include a second common bit line connected to the second electrode of the second memory element of each unit.

[0056] The first access transistors and the second access transistors may be configured so that when a specific first access transistor of a memory unit is activated via the control electrode of the specific first access transistor and when a specific second access transistor of the memory unit is activated via the control electrode of the specific second access transistor, a first logic state may be written to a corresponding first memory element of the memory unit when a first current flows from the corresponding first memory element to the first common bit line, and a second logic state may written to the corresponding second memory element of the memory unit when a second current flows from the corresponding second memory element to the second common bit line; and the second logic state may be written to the corresponding first memory element when a third current flows from the first common bit line to the first memory element, and the first logic state may be written to the corresponding second memory element when a fourth current flows from the second common bit line to the corresponding second memory element.

[0057] In various embodiments, the memory column may include a plurality of circuit arrangements or bit-cells 300 with the first bit line of each circuit arrangement 300 forming or connected to the first common bit line, and the second bit line of each circuit arrangement 300 forming or connected to the second common bit line. The memory column may include a plurality of circuit arrangements 300 with shared first and second bit lines, and shared sensing circuit. A memory unit may be one circuit arrangement or bit-cell 300.

[0058] Each memory unit may include a word line connected to the control electrode of the first access transistor and the control electrode of the second access transistor. The specific first access transistor and the specific second access transistor may be activated via the word line.

[0059] Various embodiments may provide a memory array. The memory array may include a plurality of memory columns as described herein. The memory array may also include a column multiplexer for selecting one memory column of the plurality of memory columns.

[0060] FIG. 4 shows a schematic 400 of forming a circuit arrangement according to various embodiments. The method may include, in 402, providing a first memory element having a first electrode and a second electrode. The method may also include, in 404, providing a second memory element having a first electrode and a second electrode. The method may further include, in 406, providing a first access transistor having a control electrode, a first controlled electrode and a second controlled electrode. The method may additionally include, in 408, providing a second access transistor having a control electrode, a first controlled electrode and a second controlled electrode. The method may also include, in 410, connecting a first bit line to the first electrode of the first memory element. The method may additionally include, in 412, connecting a second bit line to the second electrode of the second memory element. The method may further include, in 414, connecting the first controlled electrode of the first access transistor to the second electrode of the first memory element. The method may additionally include, in 416, connecting the first controlled electrode of the second access transistor to the first electrode of the second memory element.

[0061] The first access transistor and the second access transistor may be configured so that when the first access transistor is activated via the control electrode of the first access transistor and when the second access transistor is activated via the control electrode of the second access transistor, a first logic state is written to the first memory element when a first current flows from the first memory element to the first bit line, and a second logic state different from the first logic state is written to the second memory element when a second current flows from the second memory element to the second bit line; and the second logic state is written to the first memory element when a third current flows from the first bit line to the first memory element, and the first logic state is written to the second memory element when a fourth current flows from the second bit line to the second memory element.

[0062] In other words, the method may include forming a circuit arrangement as described herein. The method may include providing the various electrical components such as the first memory element, the second memory element, the first access transistor and the second access transistor, as well as connecting these electrical components to form the circuit arrangement as described herein.

[0063] The various steps illustrated in FIG. 4 may not be in sequence. For instance, steps 414, 416 may be carried out before steps 410, 412.

[0064] Various embodiments may a method of forming a memory column as described herein.

[0065] The method may include providing a plurality of memory units. Each memory unit may include a first memory element having a first electrode and a second electrode. Each memory unit may also include a second memory element having a first electrode and a second electrode. Each memory unit may further include a first access transistor having a control electrode, a first controlled electrode and a second controlled electrode. Each memory unit may additionally include a second access transistor having a control electrode, a first controlled electrode and a second controlled electrode. The first controlled electrode of the first access transistor may be connected to the second electrode of the first memory element. The first controlled electrode of the second access transistor may be connected to the first electrode of the second memory element. [0066] The memory column may further include connecting a first common bit line to the first electrode of the first memory element of each unit. The memory column may also include connecting a second common bit line to the second electrode of the second memory element of each unit.

[0067] Various embodiments may provide a method of forming a memory array as described herein. The method may include providing and connecting a plurality of memory columns. The method may also include providing and connecting a column multiplexer to the plurality of memory columns, wherein the column multiplexer is configured to select one memory column of the plurality of memory columns during operation.

[0068] Various embodiments may provide a method of writing to the circuit arrangement as described herein. The method may include activating the first access transistor and the second transistor. The method may include applying a potential difference so that either a first current flows from the first memory element to the first bit line, and a second current flows from the second memory element to the second bit line, or a third current flows from the first bit line to the first memory element, and a fourth current flows from the second bit line to the second memory element.

[0069] Various embodiments may provide a method of reading the circuit arrangement herein. The method may include activating the first access transistor and the second transistor. The method may include operating the circuit arrangement so that a first biasing sense current flows through the first memory element, and a second biasing sense current flow through the second memory element. The method may additionally include determining a state of circuit arrangement based on an output voltage of the sensing circuit.

[0070] Various embodiments may involve using bit line (BL) clamping devices, i.e. amplification transistors in a source-degenerated configuration during reading, which may boost the sensing margin by about severaltimes, resulting in a more reliable read.

[0071] Various embodiments may provide a more efficient read/write control, and/or lesser power. Various embodiments may provide a more compact layout, resulting in a reduced footprint, and/or lower costs. Various embodiments may offer a complete solution to high speed MRAM as an alternative to static random access memory (SRAM).

[0072] FIG. 5A shows a circuit arrangement 500 according to various embodiments. The circuit arrangement 500 may be a STT-MRAM bit-cell. The circuit arrangement 500 may include a first memory element 502, i.e. a first magnetic tunneling junction (MTJ), having a first electrode (denoted as top electrode or TE) and a second electrode (denoted as a bottom electrode or BE). The circuit arrangement 500 may also include a second memory element 504, i.e. a second magnetic tunneling junction (MTJ) having a first electrode (denoted as top electrode or TE) and a second electrode (denoted as bottom electrode or BE). The circuit arrangement 500 may further include a first access transistor 506 having a control electrode, a first controlled electrode and a second controlled electrode. The circuit arrangement 500 may additionally include a second access transistor 508 having a control electrode, a first controlled electrode and a second controlled electrode. The circuit arrangement 500 may further include a first bit line (denoted as BL) connected to the first electrode (TE) of the first memory element 502. The circuit arrangement 500 may also include a second bit line (denoted as BLB) connected to the second electrode (BE) of the second memory element 504. The first controlled electrode (e.g. drain) of the first access transistor 506 may be connected to the second electrode (BE) of the first memory element 502. The first controlled electrode (e.g. drain) of the second access transistor 508 may be connected to the first electrode (TE) of the second memory element 504. The second controlled electrode (e.g. source) of the first access transistor 506 and the second controlled electrode (e.g. source) of the second access transistor 508 may be connected to a source line (denoted as SL). The control electrode, i.e. gate, of the first access transistor 506 and the control electrode, i.e. gate, of the second access transistor 508 may be connected to a word line (denoted as WL).

[0073] MTJs 502, 504 may form a complementary pair. The circuit arrangement 500 may be referred to as a 2-transistors-2 complementary MTJ cell (2T2CM cell). The MTJs 502, 504 may store differential data (i.e. 0 and 1). The first MTJ 502 may store the true data (i.e. 0/1) while the second MTJ 504 may store the complementary value (i.e. 1/0).

» [0074] FIG. 5B is a plot 550 showing a writing operation of the circuit arrangement 500 shown in FIG. 5A according to various embodiments. The magnitude of the signals is plotted as a function of time. The voltage variations at SL and BL/BLB, as well as the resistance variation at MTJ 502 (RMTJI) and the resistance variation at MTJ 504 (RMTH) are shown in FIG. 5B as waveforms. The waveforms are stimulated using a standard complementary metal oxide semiconductor (CMOS) process and Verilog-A modeling of the MTJ elements 502, 504. Only one pair of two signals provided to SL and BL/BLB may be required for the writing operation, instead of two pairs which are required for the conventional 2T2M cell. [0075] During standby, the WL, SL, BL, and BLB may be grounded to save power. The MTJs 502, 504, may be able to retain its value due to the non-volatility of the MTJs 502, 504. During a programming phase (i.e. write operation), a WL voltage pulse may be sent to the gate of the access transistors 506, 508. The WL voltage provided during this phase may be VDD, but may alternatively be higher or lower depending on the specification of the writing speed. The access transistors 506, 508 may be activated or switched on by the WL voltage pulse at the same time.

[0076] Further, either SL or BL/BLB may be driven to a high voltage (VH) while the other may be driven to a low voltage (V _L ) to create programming or write currents flowing through the MTJs (Ip). When SL is driven to VH, BL and BLB may be driven to VL. Conversely, when SL is driven to VL, BL and BLB may be driven to VH-

[0077] The direction of programming current (I _p ) may depend on the data to be written. When writing a "1", voltage at SL (VSL) = H and voltage at BL and BLB (VBL/BLB) = VL so that the programming or write currents may flow from SL to BL/BLB.

[0078] In the first MTJ 502, a programming or write current may flow from the BE to the TE, switching the resistance to high value (RAP), while in the second MTJ 504, a programming or write current may flow from the TE to the BE, switching the resistance value to low value (Rp).

[0079] Conversely, when writing a "0", V _S L= VL and VBL/BLB = VH so that the programming or writing currents may flow from BL/BLB to SL to switch the first MTJ 502 to R _P and the second MTJ 504 to RAP.

[0080] FIG. 5C is a table 560 summarizing the writing operation of the circuit arrangement 500 shown in FIG. 5 A according to various embodiments in comparison to a conventional 2 transistors - 2 magnetic tunneling junctions cell (i.e. 2T2M cell).

[0081] FIG. 6A shows a circuit column 610 according to various embodiments. The circuit column 610 may include a plurality of memory units 600a, 600b etc. For instance, the memory unit 600a may include a first memory element or MTJ 602a having a first electrode and a second electrode, a second memory element or MTJ 604a having a first electrode and a second electrode, a first access transistor 606a having a control electrode, a first controlled electrode and a second controlled electrode, and a second access transistor 608a having a control electrode, a first controlled electrode and a second controlled electrode. The first controlled electrode of the first access transistor 606a may be connected to the second electrode of the first memory element 602a, and the first controlled electrode of the second access transistor 608a may be connected to the first electrode of the second memory element 604a.

[0082] The memory unit 600b may include a first memory element or MTJ 602b having a first electrode and a second electrode, a second memory element or MTJ 604b having a first electrode and a second electrode, a first access transistor 606b having a control electrode, a first controlled electrode and a second controlled electrode, and a second access transistor 608b having a control electrode, a first controlled electrode and a second controlled electrode. The first controlled electrode of the first access transistor 606b may be connected to the second electrode of the first memory element 602b, and the first controlled electrode of the second access transistor 608b may be connected to the first electrode of the second memory element 604b.

[0083] The memory column 610 may further include a first common bit line (denoted as BL) connected to the first electrode of the first memory element 602a, 602b of each unit 600a, 600b. The memory column 610 may also include a second common bit line (denoted as BLB) connected to the second electrode of the second memory element 604a, 604b of each unit 600a, 600b. The memory column 610 may also include a common source line (denoted as SL) connected to the second controlled electrodes of the transistors 606a, 606, 608a, 608b. The lines SL, BL, BLB may run vertically and parallel to one another.

[0084] The memory column 610 may also include a sensing circuit 612 may include a differential sensing amplifier, which may be a two stage amplifier, to determine whether a state in at least one of the first memory element 602a, 602b and the second memory element 604a, 604b of a selected memory unit 600a, 600b is the first logic state or the second logic state. The memory unit 600a, 600b to be read or sensed may be selected by providing a voltage to the control electrode of the corresponding transistors of the unit 600a, 600b to be selected. For instance, as shown in FIG. 6A, the voltage of the word line (denoted as VWL) connected to the control electrodes of transistors 606a, 608a of the memory unit 600a may be set to VDD to activate the transistors 606a, 608a to determine a state of the memory unit 600a, while the voltage of the word line connected to the control electrodes of transistors 606b, 608b of the memory unit 600b may be set to 0V so as not to select memory unit 600b for sensing or reading. [0085] The sensing circuit 612 may be configured to sense and amplify the differential signals from BL and BLB to full CMOS level.

[0086] The two stage amplifier may be connected to the first bit line and the second but line. The two stage amplifier may include a first stage 614. The first stage 614 may include or may be a common gate amplifier, which may boost an analogue potential difference between the first bit line and the second bit line to a greater value to be fed to the second stage 616, which may be or may include a latch-based sense amplifier, and which may also be comprised in the memory column 610. The two stage amplifier may provide both high-speed and large sensing margin. The sense amplifier may be used for any differential MRAM or resistive random access memory (RRAM) application, and may not be restricted to the 2T2CM cell. The sense amplifier may be used to sense any differential resistive memory cell (e.g. 2T2M) without major modification of the sensing structure.

[0087] The first stage or common gate amplifier 614 may include a first amplification transistor or boosting device 618a (denoted as NO including a control electrode, a first controlled electrode and a second controlled electrode; and a second amplification transistor or boosting device 618b (denoted as N ₂ ) including a control electrode, a first controlled electrode and a second controlled electrode. The control electrode of the first amplification transistor 618a may be connected to the control electrode of the second amplification transistor 618b at a common node.

[0088] The sensing circuit 612 may include a first current source 620a connected to the first bit line, and a second current source 620b connected to the second bit line. The first current source 620a may be configured to provide a first biasing sense current, and the second current source 620b may be configured to provide a second biasing sense current substantially equal to the first biasing sense current (denoted by I ₀ ). The first current source 620a and the second current source 620b may be arranged in a current mirror configuration so as to provide good matching.

[0089] The first controlled electrode of the first amplification transistor 618a may be connected to the first current source 620a, and the first controlled electrode of the second amplification transistor 618b may be connected to the second current source 620b. The first controlled electrode of the first amplification transistor 618a may also be connected to a first input of the latch-based sense amplifier or second stage 616 (e.g. via wire A) and the first controlled electrode of the second amplification transistor 618b may also be connected to a second input of the latch-based sense amplifier or second stage 616 (e.g. via wire B). The first input and second input of the latch-based sense amplifier or second stage 616 may be referred to as differential inputs.

[0090] The first stage may be configured to generate a first potential (at the first input of the second stage 616) based on the first biasing sense current, and further configured to generate a second potential (at the second input of the second stage 616) based on the second biasing sense current. The current sources 620a, 620b may limit the current flow through, and thus the disturbances to the MTJs.

[0091] If the first amplification transistor 618a and the second amplification transistor 618b are biased properly, the first amplification transistor 618a and the second amplification transistor 618b may each operate in saturation and may together act as a common-gate amplifier with a voltage gain from source to drain of g _m r ₀ , where g _m is the transconductance of the transistors 618a, 618b, and r ₀ is the output impedance of the current sources 620a, 620b. As r ₀ may have a very large value, a significant voltage gain may be obtained.

[0092] As shown in FIG. 6A, the voltage difference across BL and BLB may be provided by AV = I ₀ AR = I ₀ (RAP-RP), while the voltage difference across the second controlled electrodes of transistors 618a, 818b (i.e. across node A and node B) may be provided by AVi = I ₀ ARg _m r ₀ = AVg _m r ₀ . In one example, I ₀ may be about 10 μΑ, AR may be about 3kQ, and AV may be about 30 mV. While clamping devices have been used to limit the voltages along BL and BLB to protect the MTJs (bit line voltage VBL ~ clamping voltage V _c iam _P - threshold voltage V _t h), various embodiments may include transistors 618a, 618b to amplify the output. In addition, the MTJs are protected by transistors 618a, 618b which limit the voltages along BL and BLB, as well as current sources 620a, 620b, which limit the current flowing along BL and BLB.

[0093] FIG. 6B shows a plot 650 showing a reading operation of the memory column 610 shown in FIG. 6A according to various embodiments. The magnitude of the signals is plotted as a function of time. FIG. 6B shows a small AV, but a much larger AV _\ . The reading operation may start via activating the READ EN signal. The memory cell may start discharging BL and BLB. The source-degenerated clamp devices may amplify the potential difference AV to output voltage AY _\ . The second stage amplifier may be enabled (via SA EN) to obtain the voltage output. [0094] FIG. 6C shows a plot 660 of voltage (in millivolts or mV) as a function of clamping voltage (in millivolts or mV) comparing the output voltage (V _out ) and cell disturbances in terms of voltages across the magnetic tunneling junction (MTJ) in the memory column 610 according to various embodiments. FIG. 6C shows that V _ou t is large relative to the cell disturbance, and that optimum biasing may be at 570 mV. This voltage is just an indicative number and may be changed to accommodate different CMOS processes and MTJ technologies.

[0095] FIG. 7A is a schematic of a memory array 722 according to various embodiments. The memory array 722 may include a plurality of memory columns 710a-d etc. The array 722 may include a plurality of memory units or cells arranged in columns and rows. FIG. 7B is a schematic of the memory column 710a according to various embodiments. The array 722 may further include a column multiplexer (mux) for selecting one memory column of the plurality of memory columns, in addition to the sensing circuit and write driver. The column multiplexer, the sensing circuit and write driver may be denoted in FIG. 8A as 824. The array 822 may further include a row decoder 826 and a word line (WL) driver unit 828 for selecting the row of the array to write or read and driving the corresponding word line (WL). One word line may be connected to the control electrodes of the transistors of memory units or cells on the same row. Each word line may be driven by one WL driver of the WL driver unit 828. During operation, only one word line may be selected by the row decoder 826. One or more memory columns 810a-d etc. may be selected by the column multiplexer. In various embodiments, each column 810a-d may have a column switch. The array 822 may further include a control unit or control circuit 834 for synchronizing the read/write commands, clock signals, and ensuring proper operation of the array or macro 822, as shown in FIG. 8A.

[0096] Each memory column 710a-d etc. may include a sensing circuit 712 and a write driver 730, as shown in FIG. 7B. In various embodiments, a plurality of memory columns may share one sensing circuit 712 and one write driver 730. The memory column 710a shown in FIG. 7B may be similar to the memory column 610 shown in FIG. 6A. The memory column 710a may include a plurality of memory units 700a, 700b etc. Each memory unit, for instance 700a, may include a first memory element 702, a second memory element 704, a first access transistor 706, and a second access transistor 708 arranged in a 2T2CM configuration, similar to the circuit arrangement 500 shown in FIG. 5A. The sensing circuit 712 may be activated for a read operation, while the write driver 730 may be activated for a write operation. During a first write operation, the first bit line BL and the second bit line BLB may be set to VDD, while the source line SL may be set to 0 V to write the first logic state to the first memory element 702 and the second logic state to the second memory element 704. Conversely, during a second write operation, the first bit line BL and the second bit line BLB may be set to 0V, while the source line SL may be set to VDD to write the second logic state to the first memory element 702 and the first logic state to the second memory element 704. In both write operations, the current flow along BL and the current flow along BLB may be in the same direction. As such, only 1 write driver 730 may be required. The write driver 730 may include a source line and one BL/BLB driver.

[0097] The sensing circuit 712 may be a two stage differential sense amplifier as described previously. The sensing circuit 712 may include a first amplification transistor 718a (denoted by N , a second amplification transistor 718b (denoted by N ₂ ), a latch-based sense amplifier 716, a first current source 720a, and a second current source 720b. The current sources 720a, 720b may be biased by biasing voltage generator 732a, while the amplification transistors 718a, 718b may be biased by biasing voltage generator 732b. The biasing voltage generators 732a, 732b may ensure proper biasing conditions for the common- gate amplifier (i.e. amplification transistors 718a, 718b) as well as current sources 720a, 720b so that maximum output bit line voltages may be obtained to improve the sensing margin of the latch-based sense amplifier 716. The latch-based sense amplifier 716 may be used to lock the sening result and amplify the result to full CMOS level.

[0098] Various embodiments may include a pair of complementary MTJs. Various embodiments may relate to a read/write scheme to support the circuit arrangement or cell.

[0099] The 2T2CM cell may simplify the write operation and thus the write control peripheries. Various embodiments may also reduce the switching power of the SL because there may be only one SL when compared the SL and SLB of the conventional 2T2M (FIG. 2A and FIG. 5A). Various embodiments may offer large voltage gain from BL/BLB using a common-gate amplifier. The utilization of current source at each BL may ensure good gain and matching between BL and BLB. The macro or array may include voltage generators that optimize the biasing condition of the current-sources as well as the common-gate amplifier across the array. The voltage generator may be shared by the whole array and may consume minimum or little power. [00100] Due to process variations in both nano-scale CMOS and MTJ fabrication, read/write reliability may be the most critical issue in MRAM design. 1T1M cell is a design with high density, but suffers from poor read margin. As a result, 2T2M may be used to make use of differential sensing. In the 2T2M design, two sets of BL/SL driver would be used in to write MTJ1 and MTJ2 with complementary data. The BL/BLB and SL/SLB are always driven in opposite direction, which consume high switching power and requires more drivers at the read/write circuits.

[00101] Various embodiments may involve reversing the second MTJ so that the current flows would not be driven in opposing directions, thereby reducing switching power and/or silicon area, as the writing of complementary data to the MTJs without driving BL/BLB and SL/SLB in opposite directions may reduce switching power and/or silicon area.

[00102] Various embodiments may reduce switching energy during the write operation. At the same time, read operation in the 2T2CM cell may have similar requirements as in the 2T2M cell.

[00103] Various embodiments may include new read/write circuits to accommodate the new cell design, which may include new sense amplifier and/or write driver design. Various embodiments may include one or more bias generators. Various embodiments may provide an array architecture with complete read/write SRAM-like functionality.

[00104] Sensing may be critical to MRAM design. While writing may be performed with enough time, i.e. trade-off between energy/speed and write error rate, sensing may be more difficult because of excessive process variations and technology prematurity in MRAM array. MTJ may be expected to have less resistance and/or smaller programming current. It may be therefore more difficult to sense MTJs. For example, with R _P = 4 kQ, RAP = 8 kQ, Ico = 60 μΑ, read curent I _read may be around 10 μΑ - 20 μΑ to avoid read disturbance, which means a potential difference AV of < 60 mV or < 40 mV.

[00105] With process variations (for example 20% from MTJ and 20% from transistors), AV may be < 30 mV for differential design or < 11 mV for single ended design, which may mean a very low sensing margin even for differential design. Thus, there is a need to amplify this margin before latching. Various embodiments may address this issue.

[00106] Ni and N ₂ may be used to limit BL swing (i.e. bit line clamping device), but may further be properly biased to act as amplifier with a voltage gain of g _m r ₀ . This may require a good modeling of the bit-line current path, and proper biasing of the clamping device. At the same time, good current sources may also be required. Good voltage sources may be required to bias the current sources and Nj, N ₂ . Analysis also showed that there is an optimum point. Accordingly, there may be an optimum strategy for sizing and/or biasing the read circuit.

[00107] Various embodiments may provide a low write driver area, robust sensing scheme, lower power requirements (due to reduced number of write drives, fewer parasitic capacitors), and/or better sensing margins die to common access transistors. Fabrication may invilve standard fabrication steps without requiring additional masks. Further, various embodiments may involve reduced circuit complexity and a more relaxed sense amplifer design requirements due to improved noise margin of the differential signal. The design requirements and interfaces may be similar to conventional designs.

[00108] Various embodiments may be a good candidate to replace SRAM as low level cache. Various embodiments may be suitable for a large class of applications. Various embodiments may have high throughput.

[00109] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.