Title:
CIRCUIT ARRANGEMENT AND METHOD FOR CALIBRATING ACTIVATION SIGNALS FOR VOLTAGE-CONTROLLED OSCILLATORS
Document Type and Number:
WIPO Patent Application WO/2013/174377
Kind Code:
A3
Abstract:
In order to develop a circuit arrangement (100) and also a method for calibrating at least one activation signal (Vbb) provided for a voltage-controlled oscillator (10) such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed - that the respective number of clock cycles (N) for at least one calibration oscillator (50) and at least one reference oscillator (30) associated with the calibration oscillator (50) is counted by means of at least one clock cycle counter (70) connected downstream of the calibration oscillator (50) and the reference oscillator (30) and a clock error (DE) resulting from the difference between these two numbers of clock cycles (N) is integrated and - that the clock error (DE) is converted by means of at least one digital-to-analogue converter (90) connected downstream of the clock counter (70) into analogue tuning signals (Vcm, Vcm-, Vcm+) from which the calibrated activation signal (Vbb) is derived.
Inventors:
WERKER HEINZ (DE)
Application Number:
PCT/DE2013/200016
Publication Date:
January 30, 2014
Filing Date:
May 23, 2013
Export Citation:
Assignee:
SILICON LINE GMBH (DE)
International Classes:
H03L7/085; H03L7/08; H03L7/099
Foreign References:
| US7129763B1 | 2006-10-31 | |||
| US6259326B1 | 2001-07-10 | |||
| EP0739089A2 | 1996-10-23 |
Attorney, Agent or Firm:
HOFMANN, Andreas et al. (Muenchen, DE)
Download PDF: