Title:
CIRCUIT ARRANGEMENT AND METHOD OF TESTING AN APPLICATION CIRCUIT PROVIDED IN SAID CIRCUIT ARRANGEMENT
Document Type and Number:
WIPO Patent Application WO2006003596
Kind Code:
A3
Abstract:
The object being to develop an integrated circuit arrangement (100) with at least one application circuit (40) to be tested, and with at least one self-test circuit (10, 20, 32, 34, 36, 50) provided for testing the application circuit (40) and generating at least one pseudo-random test sample, wherein said pseudo-random test sample can be converted into at least one test vector that is programmable and/or deterministic and that can be supplied to the application circuit (40) for testing purposes via at least one logic gate (32, 34, 36) and by means of at least one signal that can be applied to said logic gate (32, 34, 36), and wherein the output signal arising in dependence on the deterministic test vector can be evaluated by the application circuit (40) by means of at least one signature register (50), as well as a method of testing the application circuit (40) present in the integrated circuit arrangement (100) by means of the self-test circuit (10, 20, 32, 34, 36, 50) further such that the B[uild-]I[n]S[elf-]T[est] hardware connected to the additional deterministic logic can be reduced, it is suggested that the signal to be supplied to the logic gate (32, 34, 36) can be made available by a B[it]F[lipping]F[unction] logic circuit (10) based on at least one
Inventors:
WITTKE MICHAEL (DE)
HAPKE FRIEDRICH (DE)
HAPKE FRIEDRICH (DE)
Application Number:
PCT/IB2005/052115
Publication Date:
May 11, 2006
Filing Date:
June 27, 2005
Export Citation:
Assignee:
PHILIPS INTELLECTUAL PROPERTY (DE)
KONINKL PHILIPS ELECTRONICS NV (NL)
WITTKE MICHAEL (DE)
HAPKE FRIEDRICH (DE)
KONINKL PHILIPS ELECTRONICS NV (NL)
WITTKE MICHAEL (DE)
HAPKE FRIEDRICH (DE)
International Classes:
G01R31/3187
Foreign References:
| US6061818A | 2000-05-09 | |||
| US6510398B1 | 2003-01-21 |
Other References:
TOUBA NUR A MEMBER, IEEE,; MCCLUSKEY EDWARD J LIFE FELLOW, IEEE: "Bit-Fixing in Pseudorandom Sequences for Scan BIST", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 20, no. 4, April 2001 (2001-04-01), pages 545 - 555, XP011007977
WUNDERLICH H-J ET AL: "Bit-flipping BIST", COMPUTER-AIDED DESIGN, 1996. ICCAD-96. DIGEST OF TECHNICAL PAPERS., 1996 IEEE/ACM INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 10-14 NOV. 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 10 November 1996 (1996-11-10), pages 337 - 343, XP010205403, ISBN: 0-8186-7597-7
WUNDERLICH H-J ET AL: "Bit-flipping BIST", COMPUTER-AIDED DESIGN, 1996. ICCAD-96. DIGEST OF TECHNICAL PAPERS., 1996 IEEE/ACM INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 10-14 NOV. 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 10 November 1996 (1996-11-10), pages 337 - 343, XP010205403, ISBN: 0-8186-7597-7
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