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Title:
CIRCUIT DEVICE, FREQUENCY ALTERING CIRCUIT, METHOD FOR TESTING CIRCUIT DEVICE, AND METHOD FOR CONTROLLING FREQUENCY ALTERING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2012/035651
Kind Code:
A1
Abstract:
The present invention addresses the problem of providing a circuit device that reduces test time by means of causing the frequency of a BIST clock signal to be variable. The circuit device has: a clock generating unit that outputs a clock at a first frequency; a plurality of phase control units to which the clock at the first frequency that the clock generating unit outputs is input, and that each output the clock at the first frequency at an advanced or delayed phase with respect to the phase of the clock at the first frequency; a selection unit to which the plurality of clocks at the first frequency each output by the plurality of phase control units are input, and that sequentially select the pulse of the plurality of clocks at the first frequency, outputting a clock at a second frequency; a pattern generating unit that generates a test pattern on the basis of the clock at the second frequency output by the selection unit; and a circuit unit to which the test pattern generated by the pattern generating unit and the clock at the second frequency output by the selection unit are input, and that outputs an operation result of having operated with the test pattern as the input on the basis of the clock at the second frequency.

Inventors:
KONO TAKESHI (JP)
Application Number:
PCT/JP2010/066184
Publication Date:
March 22, 2012
Filing Date:
September 17, 2010
Export Citation:
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Assignee:
FUJITSU LTD (JP)
KONO TAKESHI (JP)
International Classes:
G01R31/28; H01L21/66
Domestic Patent References:
WO2008032701A12008-03-20
Foreign References:
JP2005332555A2005-12-02
JP2006064588A2006-03-09
JP2004212310A2004-07-29
JP2005003628A2005-01-06
JP2007064648A2007-03-15
JP2004212310A2004-07-29
JP2007064648A2007-03-15
Attorney, Agent or Firm:
ITOH, TADAHIKO (JP)
Tadahiko Ito (JP)
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