Title:
CIRCUIT FOR MEETING SETUP AND HOLD TIMES OF A CONTROL SIGNAL.
Document Type and Number:
WIPO Patent Application WO/2018/191683
Kind Code:
A3
Abstract:
A circuit (300) includes series-coupled delay buffers (110a, 110b) and logic gates (310a, 310b). Each logic gate (310a, 310b) includes first and second inputs (330, 332). The first input (332) of each logic gate (310a, 310b) is coupled to a corresponding one of the delay buffers (110a, 110b). The circuit (300) also includes a plurality of flip-flops (320a, 320b). Each flip-flop (320a, 320b) includes a data input and a data output. The data input is coupled to an output (334) of a corresponding one of the logic gates (310a, 310b), and the data output is coupled to the second input (332) of one of the corresponding logic gates (310a, 310b).
Inventors:
TAFT ROBERT (DE)
Application Number:
PCT/US2018/027603
Publication Date:
November 15, 2018
Filing Date:
April 13, 2018
Export Citation:
Assignee:
TEXAS INTRUMENTS INCORPORATED (US)
TEXAS INSTRUMENTS JAPAN LTD (JP)
TEXAS INSTRUMENTS JAPAN LTD (JP)
International Classes:
H03K19/096
Foreign References:
| US7772889B2 | 2010-08-10 | |||
| US20080313485A1 | 2008-12-18 | |||
| US6731667B1 | 2004-05-04 | |||
| US20090256593A1 | 2009-10-15 |
Attorney, Agent or Firm:
DAVIS,Jr., Michael, A. et al. (US)
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