CIRCUIT MEMBER, METHOD FOR MANUFACTURING CIRCUIT MEMBER, AND SEMICONDUCTOR DEVICE COMPRISING CIRCUIT MEMBER

WIPO Patent Application WO/2007/061112

A1

Disclosed is a circuit member (20) comprising a lead frame member (1) which has a die pad portion (3), a lead portion (6) to be electrically connected with a semiconductor chip (30) and an outer frame portion (2) for supporting the die pad portion and the lead portion. The lead frame member (1) contains a resin sealing region (9). Rough surfaces (10A-C, 11A-C) having an average roughness Ra of not less than 0.3 μm are formed in the surface of the resin sealing region of the lead frame member. The lead frame member has a flat and smooth surface in the regions other than the resin sealing region. A two-layered plating layer (12A) wherein an Ni plating layer (13) and a Pd plating layer (14) are sequentially arranged, or a three-layered plating layer (12B) wherein an Ni plating layer (13), a Pd plating layer (14) and an Au plating layer (15) are sequentially arranged is formed all over the surface of the lead frame member.

SHIMAZAKI YO (JP)
SAITO HIROYUKI (JP)
MASUDA MASACHIKA (JP)
AMTSUMURA KENJI (JP)
FUKUCHI MASARU (JP)
IKEZAWA TAKAO (JP)

PCT/JP2006/323703

May 31, 2007

November 28, 2006

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DAINIPPON PRINTING CO LTD (JP)
SHIMAZAKI YO (JP)
SAITO HIROYUKI (JP)
MASUDA MASACHIKA (JP)
AMTSUMURA KENJI (JP)
FUKUCHI MASARU (JP)
IKEZAWA TAKAO (JP)

C23F1/18; C25D7/00; H01L23/28; H01L23/50

JPH0846116A	1996-02-16
JP2005079524A	2005-03-24
JPH10199905A	1998-07-31
JPH1129883A	1999-02-02
JPH09232499A	1997-09-05

YOSHITAKE, Kenji et al. (Room 323 Fuji Bldg., 2-3, Marunouchi 3-chom, Chiyoda-ku Tokyo 05, JP)

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