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Title:
CIRCUIT AND METHOD FOR MANAGING AN INRUSH CURRENT
Document Type and Number:
WIPO Patent Application WO/2018/095692
Kind Code:
A1
Abstract:
A circuit is provided for managing an inrush current of a load. The load is coupled between a voltage source and a terminal for a negative supply potential. The circuit comprises a switch that is coupled between the voltage source and the load, and that is configured to connect the load to or disconnect the load from the voltage source. The circuit further comprises at least one load capacitor coupled in parallel to the load between the switch and the terminal for negative supply potential. The circuit further comprises a control unit. The control unit comprises a sense unit and a switching unit, wherein the sense unit is configured to determine the inrush current when the switch is closed to connect the load to the voltage source, and the switching unit is configured to control the switching of the switch depending on the inrush current.

Inventors:
KARANTH, Avinash Sridhara (Schleissheimerstr. 276, Muenchen, 80809, DE)
Application Number:
EP2017/077537
Publication Date:
May 31, 2018
Filing Date:
October 27, 2017
Export Citation:
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Assignee:
HARMAN BECKER AUTOMOTIVE SYSTEMS GMBH (Becker-Goering-Str. 16, Karlsbad, 76307, DE)
International Classes:
H02H9/00; H02J1/06
Domestic Patent References:
WO2002061909A22002-08-08
Foreign References:
US20020015272A12002-02-07
US5844440A1998-12-01
Other References:
None
Attorney, Agent or Firm:
WESTPHAL, MUSSGNUG & PARTNER (Werinherstr. 79, München, 81541, DE)
Download PDF:
Claims:
1. A circuit for managing an inrush current (ic) of a load (2), wherein the load (2) is coupled between a voltage source (VI) and a terminal for a negative supply potential (GND), the circuit comprising:

a switch (SI) coupled between the voltage source (VI) and the load (2), and configured to connect the load (2) to or disconnect the load (2) from the voltage source (VI); at least one load capacitor (CL) coupled in parallel to the load (2) between the switch (SI) and the terminal for negative supply potential (GND); and

a control unit (4), wherein

the control unit (4) comprises a sense unit (42) and a switching unit (44), the sense unit (42) is configured to determine the inrush current (ic) when the switch (SI) is closed to connect the load (2) to the voltage source (VI), and

the switching unit (44) is configured to control the switching of the switch (SI) depending on the inrush current (ic).

2. The circuit of claim 1, wherein the switch (SI) comprises at least one MOSFET.

3. The circuit of claim 1 or 2, wherein the sense unit (42) comprises a sense resistor

(Rs), a sense capacitor (Cs), and a first operational amplifier (OpAmpl).

4. The circuit of claim 3, wherein

the sense resistor (Rs) and the sense capacitor (Cs) are coupled in series between the switch (SI) and the terminal for negative supply potential (GND), in parallel to the load (2); and

the first operational amplifier (OpAmpl) is configured to determine a current through the sense resistor (Rs) and to provide a sense voltage, wherein the current through the sense resistor (Rs) depends on the inrush current and the sense voltage depends on the current through the sense resistor (Rs).

5. The circuit of claim 3 or 4, wherein the switching unit (44) comprises a second operational amplifier (OpAmp2), wherein the second operational amplifier (OpAmp2) is configured to provide a switching voltage to the switch (SI).

6. The circuit of claim 5, wherein the switching voltage depends on a difference between the sense voltage provided by the first operational amplifier (OpAmpl) and a reference voltage.

7. A method for managing an inrush current (ic) of a load (2), wherein the load (2) is coupled between a voltage source (VI) and a terminal for a negative supply potential (GND), the method comprising:

providing a switching signal to a switch (SI), wherein the switch (SI) is coupled between the voltage source (VI) and the load (2) and wherein the switch (SI) is configured to connect the load (2) to or disconnect the load (2) from the voltage source (VI);

determining an inrush current (ic) through the switch (SI); and

adjusting the switching signal depending on the determined inrush current (ic).

8. The method of claim 7, wherein the switch (SI) includes at least one MOSFET having a gate terminal (G), a drain terminal (D) and a source terminal (S), and wherein the switching signal is configured to regulate a gate-source voltage (VGS) of the at least one MOSFET.

9. The method of claim 8, wherein at least one load capacitance (CL) is coupled in parallel to the load (2) between the switch (SI) and the terminal for negative supply potential (GND), wherein the at least one load capacitance (CL) is charged when the switch (SI) closes and connects the load (2) and the at least one load capacitance (CL) to the voltage source (VI), and wherein the method further comprises operating the at least one MOSFET in its linear region from a point in time when the switch (SI) closes, until the at least one load capacitance (CL) is fully charged.

Description:
CIRCUIT AND METHOD FOR MANAGING AN INRUSH CURRENT

TECHNICAL FIELD

[0001] The disclosure relates to a circuit and a method for managing an inrush current, in particular for controlling an inrush current in load switch applications.

BACKGROUND

[0002] In order to reduce the quiescent current consumption of a load, switches may be used that disconnect the load from the power supply while an operation of the load is not required. Furthermore, in many systems, capacitors are coupled in parallel to the load to ensure that there are no voltage drops on the supply rails of the load. Some systems include both, a switch for disconnecting the load from the power supply and at least one such capacitor in parallel to the load. When such a system is reactivated by closing the switch in order to apply power to the load, the capacitors will be charged which may result in an inrush current that can exceed the nominal current of the load. Excessive inrush currents, however, can cause damage to the system.

SUMMARY

[0003] A circuit is provided for managing an inrush current of a load. The load is coupled between a voltage source and a terminal for a negative supply potential. The circuit includes a switch that is coupled between the voltage source and the load, and that is configured to connect the load to or disconnect the load from the voltage source. The circuit further includes at least one load capacitor coupled in parallel to the load between the switch and the terminal for negative supply potential. The circuit further includes a control unit. The control unit includes a sense unit and a switching unit, wherein the sense unit is configured to determine the inrush current when the switch is closed to connect the load to the voltage source, and the switching unit is configured to control the switching of the switch depending on the inrush current.

[0004] A method is provided for managing an inrush current of a load. The load is coupled between a voltage source and a terminal for a negative supply potential. The method comprises providing a switching signal to a switch, wherein the switch is coupled between the voltage source and the load and wherein the switch is configured to connect the load to or disconnect the load from the voltage source, determining an inrush current through the switch, and adjusting the switching signal depending on the determined inrush current. [0005] Other systems, methods, features and advantages will be or will become apparent to one with skill in the art upon examination of the following detailed description and figures. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention and be protected by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The method may be better understood with reference to the following description and drawings. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like referenced numerals designate corresponding parts throughout the different views. [0007] Figure 1 is a schematic diagram of a circuit including a load switch for disconnecting a load.

[0008] Figure 2 is a schematic diagram of another circuit including a load switch for disconnecting a load.

[0009] Figure 3 illustrates a schematic diagram of a circuit for managing an inrush current. [0010] Figure 4 illustrates a schematic diagram of another circuit for managing an inrush current.

[0011] Figure 5 illustrates a circuit for managing an inrush current.

[0012] Figure 6 illustrates in timing diagrams several voltages and currents within the circuit of Figure 5. [0013] Figure 7 illustrates in timing diagrams several further voltages within the circuit of Figure 5. [0014] Figure 8 illustrates in a flow chart a method for managing an inrush current.

DETAILED DESCRIPTION

[0015] Figure 1 illustrates a circuit including a load 2. The load 2 is coupled between a voltage source VI and a terminal for a negative supply potential GND. A switch S 1 is coupled between the load 2 and the voltage source VI and is configured to connect the load 2 to or disconnect the load 2 from the voltage source VI . A control unit 4 is configured to control the switch S 1. The control unit 4, for example, may provide a control signal to the switch SI. Depending on the control signal, the switch SI may be opened or closed. In one example, the switch SI may be closed if the control signal has a high level and may be open if the control signal has a low level, or vice versa. This is, however, only an example. In another example, the switch S 1 may be closed when the control signal is above a threshold level and may be opened when the control signal is below the threshold level, or vice versa. The switch SI may be opened during time periods, during which an operation of the load 2 is not required. The circuit may be in a standby-mode, for example, when the switch S 1 is open. The circuit may be in an active mode, for example, when the switch SI is closed. Especially in circuits including battery powered loads, such load switches SI are often used to extend battery lifetime. While connected to the battery, the load 2 usually consumes at least a small amount of power, even if the load 2 is inactive. The use of load switches can significantly reduce quiescent current.

[0016] The circuit illustrated in Figure 2 is similar to the circuit that has been described with regard to Figure 1. The switch SI in the example of Figure 2, however, is implemented as a MOSFET (Metal Semiconductor Field-Effect Transistor). The MOSFET may be a P-channel or N-channel MOSFET that passes the voltage to the load 2, when the transistor is in an on- state. This is, however, only an example. A load switch SI may be implemented in any other suitable way. In the circuit in Figure 2, a load capacitor CL is coupled in parallel to the load 2 between the switch SI and the terminal for negative supply potential GND. The capacitor CL is configured to ensure that there are no voltage drops on the supply rails. However, when power is initially applied to the system, e.g., when the switch SI is closed to activate the load 2, this capacitor CL charges. The charging of the capacitor CL can result in an inrush current. This inrush current may be in the order of up to 100A and more. Thus, the inrush current may exceed the nominal load current. The nominal load current in this context is the maximum amount of electric current the load 2 can carry before sustaining immediate damage or deterioration.

[0017] Upon system startup (e.g., when the switch SI is closed), the power supply VI will ramp up to the regulated voltage. As the voltage increases, the inrush current flows into the uncharged capacitor CL. The amount of inrush current into the capacitor CL is determined by the slope of the voltage ramp described as follows:

Wherein ic is the amount of inrush current caused by the capacitance, CL is the capacitance of the capacitor, dV is the change in voltage during ramp up and dt is the rise time during voltage ramp up.

[0018] When the inrush current is managed or controlled, the charging of the capacitor CL becomes slower. Generally, an inrush current can be reduced by increasing the voltage rise time of the capacitor CL and thereby slowing down the rate at which the capacitor CL charges. If the voltage increases linearly, the charging current (inrush current ic) remains constant. [0019] Figure 3 illustrates an example of a circuit for managing the inrush current. The circuit generally corresponds to the circuit of Figure 2, however the control unit 4 in the circuit of Figure 3 includes a sense unit 42 and a switching unit 44. The control unit 4 is coupled to a common node between the switch S 1 and the load 2 with a first input. At its output the control unit 4 provides a switching signal to the switch SI, the switching signal being configured to switch the switch S 1 on or off (switch closed or open). The sense unit 42 and the switching unit 44 are coupled in series between the input and the output of the control unit 4. The sense unit 42 is configured to determine the inrush current ic. The switching unit 44 is configured to control the switch SI depending on the inrush current ic measured by the sense unit 42. In particular, the switching unit 44 may control the turning on of the switch SI. The switch SI may be implemented as a MOSFET, for example. In the circuit of Figure 3 the MOSFET is illustrated as an enhancement-type MOSFET. A MOSFET generally is a voltage controlled field effect transistor. A MOSFET of the enhancement-type conducts virtually no current (ID = 0), when the gate-source voltage VGS of the MOSFET is zero. When the gate-source voltage VGS reaches a threshold voltage, a drain current ID starts flowing through the MOSFET (ID > 0). The amount of current that flows through the MOSFET is dependent on the gate-source voltage VGS. Therefore, the drain current ID and thus the resulting inrush current Ic may be controlled by controlling the gate-source voltage VGS. The switching unit 44 may be configured to control this gate-source voltage VGS. For example, the MOSFET may be operated in its so- called linear region during turn-on. In this linear region the drain-source channel (D-S) of the MOSFET is conducting and is controlled by the gate-source voltage VGS. For the MOSFET to be in the linear state the gate-source voltage VGS has to be in the range of the so-called Miller voltage.

[0020] The MOSFET may be operated in its linear region until the capacitor CL is fully charged. Operating the MOSFET in its linear region, thereby providing a constant charging current to the capacitor CL, increases the time that is needed to fully charge the capacitor CL.

[0021] Figure 4 illustrates another circuit for managing the inrush current. In the circuit of Figure 4, a first capacitor CLI is coupled between the switch SI and the terminal for negative supply potential GND. An inductance LI is coupled between the load 2 and a common node between the switch S 1 and the first capacitor CLI . A second capacitor CL2 is coupled in parallel to the load 2 between the inductance LI and the terminal for negative supply potential GND. The inductance LI and the second capacitor CL2 form an LC circuit (resonant circuit). The second capacitor CL2 may be an electrolytic capacitor, for example. The use of two load capacitors CLI, CL2 is only an example. Any other number of load capacitors CLI, CL2 may be used in the circuit, depending on the application.

[0022] The sense unit 42 includes a sense capacitor Cs and a sense resistor Rs that are coupled in series. The series connection including the sense capacitor Cs and the sense resistor Rs is coupled in parallel to the first capacitor CLI between the switch S 1 and the terminal for negative supply potential GND . The sense unit 42 further includes a first operational amplifier Op Amp 1. With a first input VI, the operational amplifier Op Amp 1 is coupled to the common node between the sense resistor Rs and the terminal for negative supply potential GND. With a second input V2, the operational amplifier Op Amp 1 is coupled to a common node between the sense capacitor Cs and the sense resistor Rs. The operational amplifier Op Amp 1 is configured to determine a sense current through the sense resistor Rs. At its output VOUTI, the operational amplifier Op Amp 1 provides a sense voltage that is dependent on the sense current through the sense resistor Rs and, therefore, also on the inrush current ic.

[0023] The switching unit 44 includes a second operational amplifier OpAmp2. At a first input V3, the second operational amplifier OpAmp2 receives the sense voltage from the first operational amplifier OpAmpl. At a second input V4, the second operational amplifier OpAmp2 receives a reference voltage. The second operational amplifier OpAmp2 is configured to provide a switching voltage at its output Voun that is provided to the gate G of the MOSFET. The switching voltage depends on the difference between the sense voltage and the reference voltage. When the sense voltage is lower than the reference voltage, a switching voltage will be provided to the gate G of the MOSFET. Once the gate-source voltage VGS is greater than the threshold voltage of the MOSFET, the MOSFET conducts a current, as has been explained above. As a result, the gate-source voltage VGS decreases when the inrush current ic increases, and vice versa. When the gate-source voltage VGS decreases, this will also result in a decrease of the inrush current ic. In this way the inrush current ic can be controlled to not exceed a predetermined value.

[0024] The general function of the circuit for managing the inrush current is further described referring to Figure 5, which illustrates a simulation circuit for managing the inrush current. The circuit includes capacitors C2, C3 and C4 at the input of the load 2. The input switch (SI in Figures 1 - 4) in the circuit of Figure 5 includes 4 MOSFETs M2, M4, M5, M6. A sense capacitor C5 and a sense resistance R3 are configured to determine the inrush current, as has been explained with regard to Figure 4. The operational amplifier Ul corresponds to the first operational amplifier OpAmpl of Figure 4. The input switch M2, M4, M5, M6 is controlled by a further operational amplifier that is formed by transistors Q15 and Q16. The reference voltage of this further operational amplifier Q15, Q16 is provided by the Zener diode D2 that is coupled between one of the transistors Q15 and the terminal for negative supply potential GND.

[0025] If, e.g., R9 = 201rf2 and R4 = 10Ω, then the gain of operational amplifier Ul will be Ul = R9/R4 = 201ίΩ/10Ω = 2000. The additional operational amplifier Q15, Q16 maintains the output of operational amplifier Ul equal to its reference, e.g. 3V. For an output voltage of 3V and a gain of 2000, the second input voltage for operational amplifier Ul may be calculated as 3V/2000 = 1.5mV. A current through resistor R3, therefore, maybe calculated as 1.5mV/0.1fl = 15mA, if R3 = 0.1Ω. This current is the constant current which charges capacitor C5 to the input rail voltage. The time that is required to charge capacitor C5 at a constant current of 15mA may be calculated as T = C * V/I and, therefore, if C5 = 4.7μF, T = 4.7μF * 13V / 15mA = 4ms. This means that it will take 4ms to charge capacitor C5 at a constant current of 15mA. The charging current, which corresponds to the inrush current, may generally be calculated as I = C * V/T. Therefore, if C2 = C3 = C4 = 560μF, ic = 560μF * 3 * 13V / 4ms = 5.5A. The values in this example, however, are only exemplarily chosen. Any other suitable values may be chosen for the components within a circuit for managing the inrush current. [0026] It can be seen from the results described above that even if supply rail (node KL30) rises sharply, the voltage at the electrolytic capacitors C3, C4, C5 (node KL30 SW) rises much more slowly. The time that is needed to fully charge the capacitors C3, C4, C5 (rise time at node KL30 SW) is about 4ms, as has been calculated above. The charging current through resistor Rl is about 5.5A. The output of operational amplifier Ul is maintained at about 3V. During the 4ms that are needed to charge the capacitors C3, C4, C5, the MOSFETs M2, M4, M5, M6 are driven in their linear region and, therefore, limit the inrush current. In the current example this can be seen as a voltage of about 3 V at the GATE of the MOSFETs M2, M4, M5, M6. When, after about 4ms the capacitors C2, C3, C4 are fully charged, the output of the operational amplifier Ul reduces and the further operational amplifier Q15, Q16 increases its output voltage, trying to maintain the output of operational amplifier Ul equal to the reference voltage. This increases the gate-source voltage of the MOSFETs M2, M4, M5, M6 and turns the MOSFETs M2, M4, M5, M6 fully on. These results demonstrate that as a result the voltage between nodes KL30 and KL30_SW reduces slowly (while the MOSFETs M2, M4, M5, M6 are in linear mode) and finally reaches zero after about 4ms when the capacitors C2, C3, C4 are fully charged (MOSFETs M2, M4, M5, M6 are fully on).

[0027] This is further illustrated in the diagrams in Figures 6 and 7. The first diagram in Figure 6 (topmost diagram) illustrates the voltage at node KL30 (V (KL30)) over time. As can be seen, the voltage V(KL30) immediately rises to a maximum voltage, which is about 13 V in the circuit of Figure 5. The voltage at node KL30 SW (second diagram from top), however, is regulated and rises linearly for about 4ms until the capacitors C2, C3, C4 are fully charged. When the capacitors C2, C3, C4 are fully charged, the voltage V(KL30_SW) reaches its maximum value at about 13V. The current I(R1) at resistor Rl (third diagram from top) shows a peak shortly after the voltage at node KL30 rises to its maximum value and then stays constant at a value of about 5.6A until the capacitors C2, C3, C4 are fully charged. When, after about 4ms, the capacitors C2, C3, C4 are fully charged, the current I(R1) falls back to OA. The voltage V(OUT) at the output of operational amplifier Ul, after a short peak, levels to a value of about 3.0V until the capacitors C2, C3, C4 are fully charged, when it falls back to zero.

[0028] Figure 7 illustrates again the voltage V(KL30_SW) at node KL30_SW (topmost diagram) and the voltage V(OUT) at the output of operational amplifier Ul , as described above (second diagram from top). The voltage V(GATE) at node V(GATE, SOURCE) between the gate terminal G and the source terminal S of the MOSFET (third diagram from top) rises to about 3 V (level of Miller voltage of MOSFET) while the capacitors C2, C3, C4 are charged (linear mode of MOSFETs M2, M4, M5, M6). When the capacitors C2, C3, C4 are fully charged, the voltage V(GATE) at node GATE rises to its maximum value of about 13 V. The voltage V(KL30, KL30 SW) (fourth diagram from top) between node KL30 and node KL30 SW in contrast, rises to a maximum value of about 13V directly after the voltage at KL30 rises to its maximum value and decreases to zero while the capacitors C2, C3, C4 are charged.

[0029] Figure 8 illustrates in a flow chart a method for managing an inrush current. A switching signal is provided to a switch (step 800). The switch is coupled between a load and a voltage source and is configured to connect the load to or disconnect the load from the voltage source. When the load is connected to the voltage source, a current is provided to the load and the circuit is in an active mode. When the switch is open and the load is not connected to the voltage source, no current is provided to the load and the circuit is in an inactive or standby-mode. When the switch is closed, an inrush current through the switch arises. This inrush current is determined (step 802). Depending on the determined inrush current, the switching signal is adjusted (step 804). In this way, the current through the switch can be controlled and an excessive inrush current can be prevented.

[0030] While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the invention. Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents.