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Title:
CIRCUIT AND METHOD FOR REDUCING INTERFERENCE OF POWER ON/OFF TO HARDWARE TEST
Document Type and Number:
WIPO Patent Application WO/2020/042740
Kind Code:
A1
Abstract:
A circuit and a method for reducing interference of power on/off to hardware test. The power on/off control function of an original mechanical switch is reserved; an original scheme is compatible in operation; only simple components are added to the circuit, the structure is simple and easy to implement. Without adding any new operation method, the existing test process can be directly imported. In the circuit, isolated power supply modules, RC time delay circuits, and MOSFET are connected in a reverse-serial manner. At the moment when a switch is turned on, the gate voltage of each MOSFET increases slowly in a sloping manner due to the effect of the RC time delay circuits, and the MOSFET is switched on gradually; and at the moment when the switch is turned off, the grid voltage of each MOSFET decreases slowly in a slopping manner due to the effect of the RC time delay circuits, and the MOSFET is switched off gradually, so that the interference of electric sparks caused by the critical state when the mechanical switch is powered on/off to hardware test can be eliminated, an oscilloscope would not capture electric spark signals when a boardcard is not powered on/off stably, thereby increasing the test efficiency.

Inventors:
GE ZHIHUA (CN)
Application Number:
CN2019/093324
Publication Date:
March 05, 2020
Filing Date:
June 27, 2019
Export Citation:
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Assignee:
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD (CN)
International Classes:
G01R13/00; G01R31/26
Foreign References:
CN109142821A2019-01-04
CN208780742U2019-04-23
CN206281909U2017-06-27
CN103701163A2014-04-02
CN103053003A2013-04-17
TW201131924A2011-09-16
KR20090109936A2009-10-21
Attorney, Agent or Firm:
UNITALEN ATTORNEYS AT LAW (CN)
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