Title:
CIRCUIT FOR MULTIPLEXING MON PIN OF RECEIVER OPTICAL SUB-ASSEMBLY FOR OPTICAL COMMUNICATION
Document Type and Number:
WIPO Patent Application WO/2019/140740
Kind Code:
A8
Abstract:
Provided in the invention is a circuit for multiplexing an MON pin of an optical receiver sub-assembly for optical communication. Drain potential of PMOS transistors M0 and M1 in a current mirror is kept equal through utilization of a first clamp circuit, thereby keeping the high precision of a whole monitoring dynamic range. After flowing out through the MON pin, a monitoring current flows into an NMOS transistor M3 and is converted into a gate voltage of the M3, and the gate voltage is input into a first analog to digital converter and then is converted into digital quantity, thereby realizing a current monitoring function. Through utilization of a second clamp circuit, a voltage of the MON pin is clamped into an input voltage Vcont_in of the second clamp circuit, so a voltage Vcont _out of the MON pin is read in a trans-impedance amplifier. In this mode, an external control signal Vcont_in is copied and input into the trans-impedance amplifier, and then the Vcont_in is converted into various control variables through a comparator or the analog to digital converter. Thus, multiplexing of the MON pin is achieved.
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Inventors:
LIN SHAOHENG (CN)
Application Number:
PCT/CN2018/077384
Publication Date:
June 04, 2020
Filing Date:
February 27, 2018
Export Citation:
Assignee:
XIAMEN UX HIGH SPEED IC CO LTD (CN)
International Classes:
H04B10/69; H03F3/08; H03F3/45
Attorney, Agent or Firm:
XIAMEN SHINHWA PATENT & TRADEMARK AGENCY CO., LTD. (CN)
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