Title:
CIRCUIT FOR RECOVERING A DATA SIGNAL AND REGENERATING A CLOCK SIGNAL
Document Type and Number:
WIPO Patent Application WO2000018008
Kind Code:
A3
Abstract:
According to the invention, the circuit for recovering a data signal and regenerating a clock signal can be fully integrated into a chip and has two independent series-mounted PLL regulating steps (2, 6) that can be optimally adjusted in a separate manner. The first regulating step (2) has a wide bandwidth and is optimized for the highest possible jitter tolerance. The second regulating step (2, 6) has a narrow bandwidth and is optimized for the lowest possible jitter transfer. The circuit can be used, for example, in transceivers for ATM, SONET and SDH applications with Gbit signal transmission links.
Inventors:
FRIEDRICH DIRK (DE)
ROZMANN MICHAEL (DE)
ROZMANN MICHAEL (DE)
Application Number:
PCT/DE1999/002742
Publication Date:
May 25, 2000
Filing Date:
September 01, 1999
Export Citation:
Assignee:
SIEMENS AG (DE)
FRIEDRICH DIRK (DE)
ROZMANN MICHAEL (DE)
FRIEDRICH DIRK (DE)
ROZMANN MICHAEL (DE)
International Classes:
H03L7/07; H03L7/087; H03L7/08; H04L7/033; (IPC1-7): H04L7/033; H03L7/07
Domestic Patent References:
| WO1998010519A1 | 1998-03-12 |
Foreign References:
| GB1531632A | 1978-11-08 |
Other References:
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 02 30 January 1998 (1998-01-30)
PATENT ABSTRACTS OF JAPAN vol. 012, no. 395 (E - 671) 20 October 1988 (1988-10-20)
PATENT ABSTRACTS OF JAPAN vol. 012, no. 244 (E - 631) 9 July 1988 (1988-07-09)
PATENT ABSTRACTS OF JAPAN vol. 012, no. 395 (E - 671) 20 October 1988 (1988-10-20)
PATENT ABSTRACTS OF JAPAN vol. 012, no. 244 (E - 631) 9 July 1988 (1988-07-09)
Download PDF: