MULTI−STABLE CIRCUIT

WIPO Patent Application WO/2003/028214

A1

A multi−stable circuit capable of outputting a voltage or potential depending on its stable state and used for a multivalue memory cell, a multivalue memory, multivalue storage means, a multivalue logic circuit, a multivalue computer, multivalue control means, and so on. For example, in the case of a 10−stable circuit, the potential rises gradually from a power line (V1) to a power line (V10), 'pull−down means having negative resistance characteristics' is connected between the power line (V1) and an input&sol output terminal (Tio), 'bi−directional pull means bi−directionally having the negative resistance characteristics' is connected between each of the power lines (V2) to (V9) and the input&sol output terminal (Tio), and 'pull−up means having the negative resistance characteristics' is connected between the power line (V10) and the input&sol output terminal (Tio). The negative resistance characteristics are the 'negative resistance characteristics in which the resistance decreases as the terminal voltage decreases and in which the resistance increases as the terminal voltage increases'. The use of eight bi−directional pull means shortens the reading time while eliminating unfeasible read, transition of the stable state in reading, and any read error.

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SUZUKI TOSHIYASU (JP)

PCT/JP2001/008121

April 03, 2003

September 19, 2001

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SUZUKI TOSHIYASU (JP)

H03K3/038; H03K3/3565; H03K3/3568; (IPC1-7): H03K3/027; H03K3/29

JP2000083369A

2000-03-21

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