BACKGROUND OF THE INVENTION For sake of illustration, let us consider a conventional ANN built with specific neurons, referred to in the technical literature as the ZISC neurons (ZISC is a registered trademark of IBM Corp.). US patent N° 5,621,863 describes the ZISC neuron architecture while US patent N° 5,717,832 is more particularly directed to the architecture of a ZISC ANN that is integrated in a silicon chip. Both US patents are assigned to IBM Corp. In essence, a ZISC ANN integrated in a silicon chip includes means to receive input pattern components and global resources from a host computer (or controller) or the user and means to store them, control logic means coupled to the host computer/user to timely perform the different processing steps that are necessary for a proper ANN operation, a plurality of ZISC neurons and finally a number of buses to connect said means with each neuron of said plurality and to interconnect

neurons between them. By global resources it is meant the category, the MaxIF/MinIF, and the context/norm using the terminology adopted in the aforementioned US patents, but other parameters could be used as well. Note that MaxIF and MinIF are the maximum and the minimum values of the AIF (Actual Influence Field) respectively. In turn, each ZISC neuron contains a Weight memory (a RAM) to store the components of an input pattern as a prototype that is required in both the learning and recognition phases, a Category register to store the category assigned to the prototype, the Context/Norm register to store the global context/norm, the AIF register to store any intermediate value between MaxIF and MinIF as a result of the AIF reduction process and finally the Distance register. When stored in a ZISC neuron, said global resources mentioned above thus become local resources.

At initialization, none of the ZISC neurons having learned, they are all"free". As soon as a neuron has learned an input pattern, i. e. the input pattern components are stored in the Weight memory to represent the components of the prototype attached to this neuron, it is no longer free, it is said "engaged". In order to reduce the number of clock cycles needed for loading an input pattern presented to the ANN once the ANN has decided to store it as a prototype, this input pattern is pre-charged in the first free neuron during the input pattern presentation. To implement this important feature, a "pre-charge circuits described in details in US patent 5,701,397 assigned to IBM Corp. This pre-charge circuit closely works with another essential circuit, referred to as the"daisy chain circuit", which is described in details in US patent N° 5,710,869 still assigned to IBM Corp. The daisy chain circuit indicates the state of each neuron: first free or engaged and its role is to structure the ANN as a chain of neurons working in parallel.

In ANNs built with standard ZISC neurons, only the input pattern components are pre-charged in the Weight memory of the

first free (or"ready to learn") neuron via a dedicated bus during the learning phase. If the input pattern is learned, this first free neuron is then declared as being engaged (or committed) and the said dedicated registers in this neuron are loaded with global resources (category, global context,...) to create the local resources mentioned above. As a matter of fact, the Category register is loaded with the category emitted by the host computer/user via the Cat bus. The Context/Norm register and the AIF register are updated via two buses: the Context/Norm bus and the MaxIF/MinIF bus respectively. The AIF Register is loaded via the MaxIF/MinIF bus. Note that the distance is not loaded in the Distance register during the learning phase because the distance is only evaluated during the recognition phase.

To facilitate reader's understanding, the above comments will be now illustrated by reference to Fig. 1 which schematically shows the architecture of a ZISC ANN and the basic data transmission principles to apply the input pattern components and the global resources to the standard ZISC neurons such as disclosed in US patent 5,621,863 including the pre-charge and the daisy chain features mentioned above.

Now turning to Fig. 1, the architecture of a simplified ANN referenced 10 including a plurality of ZISC neurons 11-1 to 11-n and some global resources that are common to all the neurons, i. e. data that must be simultaneously applied to all the neurons of the ANN. The global resource is either stored in a register (e. g. the Context register), or sent by the host computer/user (e. g. the category) before being transmitted to the neurons. For the sake of simplicity, the registers lodged in each neuron that are mentioned herein have not been shown in Fig. 1. Each standard ZISC neuron, e. g. 11-1, incorporates a daisy chain circuit, e. g. 12-1, to distinguish its state as indicated above. Five data buses labeled 13 to 17 are used to convey various types of data to the said plurality of neurons.

The Comp bus 13 transports the input pattern components to

pre-charge them in the first free neuron. As soon as an input pattern is stored in the first free neuron as a prototype, a category is assigned to it via the Cat bus 14. The MaxIF which is required in each neuron during the learning is stored in the AIF register via the MaxIF/MinIF bus 15. MinIF which is required in a very few cases is made available in each neuron whenever necessary thanks to multiplexer 18 depending upon a control signal (not shown) generated by the control logic circuit 19. Likewise, to perform any basic operation during the learning or recognition phase, each neuron must know the global context/norm value (this value can be changed at any time) which is usually stored in the global Context/Norm register.

Context/Norm bus 16 is used to that end to apply this common value to all neurons 11-1 to 11-n for local storage thereof, but it is also used for comparison purposes to compare the global context value and the local context value. If the global context matches the local context, the neuron is said "Selected", i. e. it is allowed to participate to the recognition of input patterns. Finally, a fifth bus, labeled Add/Ctl bus 17, interconnects the Control logic circuit 19 with each of said plurality of neurons. It transports the necessary addresses and control signals under host computer/user supervision. Still considering Fig. 1, there is schematically shown some signals that are related to any daisy chain circuit 12. DCI represents the state of the previous neuron in the chain, DCO represents the state of the neuron in consideration.

Signals CO (stands for COmmitted) and RS (stands for Ready to Store) are bits that indicate if the neuron in consideration is engaged (e. g. CO = 1 and RS = 0) or is the first free neuron (CO = 0 and RS = 1). Note that, the notations used to designate the different elements shown in Fig. 1 are substantially the same as the notations used in the aforementioned US patents or can be easily derived therefrom.

As apparent in the ANN architecture shown in Fig. 1, four buses 13 to 16 are thus required to transport the input pattern components (for pre-charge in the first free neuron) and the

global resources (category, MaxIF/MinIF, and context/norm) to load them in the corresponding local registers still of the first free neuron as soon as the ANN has decided to learn the input pattern. The conventional architecture 10 of Fig. 1 is not satisfactory in some respects.

As known for those skilled in the art, because a ZISC ANN may include a very large number of standard ZISC neurons (up to 1000 and even more), the complexity of the interconnect network can dramatically increase, as a result of the length increase of the buses 13-17. In turn, it is required to design either a few very big drivers (or a great number of small drivers) to supply the high current levels that are needed. Besides the room necessary to integrate such big drivers in the silicon chip, there is also a not negligible risk of failures in making so important network of electric wires at the silicon chip surface.

Reducing the number of buses used to perform the desired connections/interconnections at the silicon chip surface is therefore the primary factor to day to improve ANN performance.

The solution which consists to transmit data in a serial way on a single bus whenever possible (or at least on a limited number of buses) is not satisfactory in term of transmission delays.

Because many changes occur in the value of said global resources during the learning and recognition phases, many updates of the local registers in the neurons are required. As a result, the buses are very busy so does the control logic circuit, so that the ANN wastes a lot of time to perform the global resource update tasks due to the increased number of clock cycles that is required in the control logic circuit 19.

In the instant case of the conventional ANN architecture depicted in Fig. 1 that includes standard ZISC neurons, a compromise solution was retained by the circuit designers to convey data representing the input pattern component and the global resources to all the neurons of the ANN. In this particular case, some data are serially transmitted (e. g. the

input pattern components) some other are transmitted in parallel (e. g. the global context).

More generally, in architectures based on parallel-like computing (such as ZISC ANNs) and in massively parallel computers, very fast computations are obtained because a large number of neurons or elementary processors are connected in parallel for simultaneous processing. As a result, parallel-like or parallel architectures are much appreciated to date for very fast data processing. In such parallel-like or parallel architectures, the neurons or the elementary processors must be connected to each other or to global resources that are common for all. As a consequence, the number of buses and the complexity of the interconnect network can become extremely high.

Therefore, to significantly increase performance of parallel-like or parallel system architectures, it is thus highly desired to optimize each neuron or elementary processor in terms of bus number, connect/interconnect network complexity and processing time.

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a circuit for pre-charging different global resources (category, context, MaxIF/MinIF and the like as well) in dedicated registers of all the free neurons of the ANN during the learning and the recognition phases.

It is another object of the present invention to provide a circuit for pre-charging different global resources in dedicated registers of all the free neurons of the ANN during the learning and the recognition phases via a single bus and a selector under control logic circuit supervision.

It is another object of the present invention to provide a circuit for pre-charging different global resources in dedicated registers of all the free neurons of the ANN during the learning and the recognition phases which allows a significantly reduction of the number of buses without increasing the number of clock cycles required by the control logic circuit to update the local resources.

It is another object of the present invention to provide a circuit for pre-charging different global resources in dedicated registers of all the free neurons of the ANN during the learning and the recognition phases which requires a minimum number of elementary logic circuits/gates.

It is still another object of the present invention to provide an improved daisy chain circuit that is adapted to work with said circuit for pre-charging different global resources in dedicated registers of all the free neurons of the ANN during the learning and the recognition phases by indicating which neurons are free.

It is still another further object of the present invention to provide the architecture of an improved ZISC neuron that is adapted to store different global resources via a single bus as corresponding local resources and the architecture of an ANN incorporating a plurality of such improved ZISC neurons.

According to the present invention there are described a method and circuits to maintain an exact and permanent correspondence between different global resources and corresponding local resources stored in dedicated registers placed in all the neurons that are free. Global resources (category, MaxIF/MinIF, context/norm,...) are applied on a single bus common for all global resources, referred to as the Data bus, via a selector, which is under supervision of the control logic circuit of the ANN. In turn, the Data bus is connected in parallel to said dedicated registers in all neurons. Each dedicated register is

controlled by its own Write Enable (WE) signal. The WE signal is generated by a pre-charge circuit comprised of an address decoder connected to said control logic circuit via an address/control bus, referred to as the Add/Ctl bus, and an AND gate which receives the output of said address decoder on a first input and a FREE signal generated by a daisy chain circuit on the other input. The role of the FREE signal is to indicate whether the neuron is free or not.

When a global resource is updated by the host computer/user, an identifier, typically an address, is sent to the control logic circuit. The selector applies the updated value on the Data bus and simultaneously, the control logic applies this address (or an address related thereto) on the Add/Ctl bus to identify which global resource is being sent to all neurons. The WE signal enables only the corresponding dedicated register of all the free neurons to load said updated global resource therein as a local resource.

Because, the method and circuits of the present invention allows to maintain an exact and permanent correspondence between global resources and corresponding local resources, it is no longer necessary to load the global resources at each learning of a neuron, since they are already pre-loaded.

Therefore, the proposed solution allows to reduce the number of input buses (in the present case only two buses are now necessary instead of the 5 buses previously used in the standard ZISC ANN) without increasing the number of clock cycles The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows the architecture of a conventional ANN constructed with standard ZISC neurons to emphasize the role of the four input buses that are necessary to distribute the input pattern components and the different global resources to all the neurons of the ANN.

Fig. 2 shows the architecture of the ANN that now only requires one bus and a selector to distribute the input pattern components and the different global resources to all the neurons of the ANN according to the present invention.

Figs. 3A, 3B and 3C show the contents of two global registers and corresponding local registers for four neurons of an ANN respectively after reset, learning and MaxIF updating.

Figs. 4A and 4B show the data flowchart for two global resources, MaxIF and context respectively, to illustrate the method of the present invention.

Fig. 5 shows the innovative daisy chain circuit placed in each improved ZISC neuron which is adapted to generate a signal indicating whether the neuron is free or not according to the present invention.

Fig. 6 shows the innovative pre-charge circuit placed in each neuron for pre-charging one global resource in the corresponding dedicated register of all the improved ZISC neurons of the ANN that are free according to the present invention.

Figs. 7A and 7B respectively show a more detailed construction of the pre-charge circuit of Fig. 6 when it is adapted to process the MaxIF and the global context.

Fig. 8 shows a more detailed construction of the pre-charge circuit of Fig. 6 when it is adapted to process both the MaxIF and the global context in a single circuit.

DESCRIPTION OF A PREFERRED EMBODIMENT In accordance with the principles at the base of the present invention, there is continuously maintained an exact and permanent correspondence between the different global resources (category, MaxIF/MinIF, and context/norm) and the respective local resources in all the neurons of the ANN that are free. To that end, innovative circuits are placed in each standard ZISC neuron, now referred to as an improved ZISC neuron. When, during a learning or a recognition phase, a global resource is updated, a selector which receives each of said global resources as an input signal applies said updated global resource on a single data bus that is thus adapted to transport all said global resources and the input pattern components upon control logic circuit supervision. The control logic circuit applies a specific address on the Add/Ctl bus 17 to pre-charge the updated global resource in the corresponding dedicated register of all the free neurons of the ANN for local storage.

This address, referred to as the Address, is the same or is related to the address emitted by the host computer/user, referred to as the ADDRESS, to identify the global resource.

Each neuron includes an innovative pre-charge circuit, the main element of which is a specific address decoder and a new daisy chain circuit that is now adapted to generate a signal to identify all the free neurons in the ANN. Note that an address decoder already exists in each standard ZISC neuron, but it has been implemented for a different purpose, for instance, to address the local AIF register when a determined neuron must be accessed. The innovative pre-charge and daisy chain circuits of the present invention that are placed in each improved ZISC neuron thus allows to load a global resource in all the free neurons as soon as it is updated. As a result, although a

global resource can be modified at any time, for all the free neurons of the ANN, there will be a permanent and exact correspondence between each of the global resources and its corresponding local resource stored in a dedicated register. As far as the pre-charge of the input pattern components in the first free improved ZISC neuron is concerned, there is no significant change with respect to the standard ZISC neuron, except that there is no longer a specific Comp bus to transport them, but said single data bus will be used instead.

Fig. 2 illustrates this new approach. Turning to Fig. 2, there is shown the architecture referenced 20 of an ANN built with improved ZISC neurons now referenced 11'-1 to ll'-n. When compared with the ANN architecture 10 depicted in Fig. 1, there are some significant changes in the distribution of the data.

As apparent in Fig. 2, each global resource (category, MaxIF/MinIF, context/norm) and the input pattern components are applied to a selector referenced 18'. As soon as a global resource is updated, the updated global resource is sent on a common bus, labeled Data bus and referenced 13', via selector 18'under supervision of the control logic circuit 19. Each neuron, e. g. 11'-1, is provided with an innovative daisy chain circuit, e. g. 12'-1 that is capable to generate a FREE signal indicating whether the neuron is free or not and a pre-charge circuit, e. g. 21-1, adapted to enable the loading of the global resource that is present on the Data bus 13'. It is the role of control logic circuit 19 to apply the adequate Address on the Add/Ctl bus 17 to perform said loading of the global resource in the corresponding register of all the improved ZISC neurons that are free where it becomes a local resource. In the ANN architecture 10 of Fig. 1, the ADDRESS related to a determined global resource, e. g. MaxIF, that was sent by the host computer was only used to load this global resource in its corresponding global register (if any), e. g. the MaxIF global register. But now, this ADDRESS will be exploited by the control logic circuit 19, which in turn emits an address derived therefrom, referred to as the Address, used to load this global resource

in the AIF register of all the neurons of the ANN that are free. In other words, this Address permits to identify the nature of the global resource that is present on the Data bus 13' (remind that it is designed to transport all the global resources).

Figs. 3A, 3B and 3C respectively show the content of two global registers containing global resources: MaxIF and global context for the first four improved ZISC neurons 11'-1 to 11'-4 (for the sake of simplicity) after reset, learning an input pattern and a MaxIF update operation.

Now turning to Fig. 3A, there is shown a partial configuration of ANN 20 after the reset operation. The FREE signal is high (FREE = 1) to indicate that the four neurons are free. Global resource registers are set to the default values, for example MaxIF is set to 1000 and the global context is set to 0. The reset operation comprises several steps using the Data bus 13' to load said values into the corresponding local registers of said four free neurons, i. e. the AIF register and the Context/Norm register, referred to hereinbelow as the CXT register for the sake of simplicity.

Fig. 3B shows the status of the Fig. 3A configuration after a learning phase so that some neurons have been engaged, in this case, two neurons. For these two engaged neurons 11'-1 and 11'-2, the FREE signal is set to 0 while for the two free neurons 11'-3 and 11'-4 the FREE signal is still set to 1. As all the neurons have their AIF set to 1000 except neuron lu'-2 for which it is assumed that its AIF has been reduced to 800 during a reduction process (internal). Note that, during the learning phase, none clock cycle is required to transmit the AIF and the global context values because they were already loaded after the reset operation.

Fig. 3C shows the Fig. 3B configuration after an update of the MaxIF value to 50. The content of the local AIF register in the

two free neurons 11'-3 and 11'-4 is updated. Because, this change from 1000 to 50 occured during the update operation of the global resource, no extra time was required.

Now, should a new neuron be engaged, necessarily the first free (e. g. 11'-3), it would have the local Context (CXT) register set to 0 and the AIF register set to 50 (if no more reduction has occured in the meantime).

Fig. 4A shows the flow chart referenced 22 for an update of the MaxIF value. This flow chart explains how to maintain an exact correspondence (mirror effect) between the MaxIF value (a global resource) and the content of the AIF register (a local resource) in all the free neurons. First of all, for each update operation, a test is made in block 23 to determine if the global resource is MaxIF based upon the ADDRESS (assigned to each global resource by the host computer as mentioned above). If yes, this MaxIF value is stored in the MaxIF register as a global resource (block 24) and the MaxIF value is made available to all the neurons of the ANN through a single bus, the Data bus 13' (which according to the present invention transports all the global resources) and the Address is applied on the Add/Ctl bus 17 (block 25). Then, the following process is started for each neuron. In each neuron, the Address is tested in block 26, if this Address does not match with a MaxIF update, it is not needed to also update the content of the local resource (AIF register). On the contrary, if this address corresponds to a MaxIF update, the local value must be updated to have the desired mirror effect between the global and local resources, only if the neuron is free. Therefore, the state of the neuron is tested in block 27 and if found free, the content of the AIF register is updated with MaxIF in block 28.

Fig. 4B shows the process flow chart 29 for an update of the global context. Likewise, this flow chart explains how to maintain an exact correspondence (mirror effect) between the global context resource and the contents of the local Context

registers in all the free neurons. First of all, for each update operation, a test is made in block 30 to determine if the global resource is the global context based upon the ADDRESS. If yes, this global context value is stored in the global Context register as a global resource (block 31) and the global context is made available to all the neurons of the ANN through Data bus 13'and the Address is applied on the Add/Ctl bus 17 (block 32). Then the following process is started for each neuron. In each neuron the Address present on the Add/Ctl bus 17 is tested in block 33, if this address does not match with a global context update, it is not needed to update the content of the local resource (Context register). On the contrary, if this address corresponds to a global context update, the local value must be updated to have the desired mirror effect between the local and global resources, only if the neuron is free. Therefore, the state of the neuron is tested in block 34 and if found free, the content of the Context register is updated with the global context in block 35. However, because it is necessary for engaged neurons to compare the content of the local Context (CXT) register with the content of the global Context register in order to set the flag"Selected", needed in the control logic circuit, a comparison in made in block 36.

Fig. 5 shows the innovative daisy chain circuit placed in each improved ZISC neuron according to the present invention which is now adapted to generate a signal (FREE) indicating whether the neuron is free or not. The FREE signal is thus different from the RS signal generated by the daisy chain circuit placed in the standard ZISC neuron which only flags the first free neuron in the chain.

Now turning to Fig. 5, the innovative daisy chain circuit 12' is still serially connected between the two adjacent daisy chain circuits of the previous and next improved ZISC neurons, so that all the neurons of the ANN form a chain. The daisy chain circuit 12 is basically identical to circuit 600

described in the aforementioned US patent 5,710,869. It is built around a 1-bit register 37 controlled by a store enable signal (ST) which is active at initialization or during the learning phase when a new neuron is engaged. The DCI signal is applied to the first input of a two-way AND gate 38 whose other input receives the RESET_ signal. The output of AND gate 38 is connected to the input of register 37. The output of register 37 is connected to a 2-way OR gate 39 which receives the ALL signal on its other input. The DCO signal is available at the output of OR gate 39. Circuit 12'still includes a control logic block referenced 40 which consists of a 2-way XOR and 2-way AND gates referenced 41 and 42 to generate the RS and CO signals respectively. Gate 41 performs the XORing of signals DCI and DCO and gate 42 performs the ANDing of signals DCO and NS (NS is high for a selected neuron). The novelty consists in the addition of inverter 43 in block 40 which is connected to the output of register 37 and generates the FREE signal which is essential to implement the present invention. The operation of daisy chain circuit 12'is thus substantially the same as circuit 600. The following table illustrates the different neuron states as a function of the DCI/DCO signal combinations.

TABLE DCI DCO State FREE RS CO 0 0 free 1 0 0 1 0 first free 1 1 0 1 1 engaged 0 0 1 0 1 reserved--- FIG. 6 schematically shows the partial architecture referenced 44 of an ANN built with improved ZISC neurons. Now turning to Fig. 6, the global resources are grouped in a block 45 shown in dotted line, usually stored in registers, the outputs of which are connected to selector 18' (see Fig. 2). Fig. 6 further shows a local dedicated register 46 and a block 47 comprised of

the innovative pre-charge and daisy chain circuits of the present invention referenced 21 and 12'respectively (see Fig.

2). The role of pre-charge circuit 21 is to enable the global resource present on the Data bus 13' (which transports all the global resources without distinction) to be loaded into the local register 46. As a result, there are as many blocks 21 in a neuron as there are local registers to be loaded with a global resource, in this case three (category, context/norm and MaxIF/MinIF). Still referring to Fig. 6, the Data bus 13'is connected to local register 46 either directly or, optionally, via a multiplexor if some internal data can be also loaded therein for some specific applications. Pre-charge circuit 21 is essential in that it generates a signal WE (stands for Write Enable) synchronized with the global resource update that allows or not to load the global resource in the local register 46. Pre-charge circuit 21 consists of an address decoder 49 which decodes the Address (present on the Add/Ctl bus 17) attached to each global resource and of a 2-way AND gate 50.

Decoder 49 is connected to the control logic circuit 19 via the Add/Ctl bus 17. Its output is connected to a first input of AND gate 50, the other input receives the FREE signal from the daisy chain circuit 12'. When the address decoder 49 recognizes an Address on the Add/Ctl bus 17 matching the global resource present on Data bus 13', the signal output by decoder 49 is active, e. g. equal to 1 and if the FREE signal is also high (FREE = 1), the WE signal will be high for this free neuron allowing thereby to load the global resource in register 46. As a result, the WE signal thus determines when the content of the local register 46 must be changed to meet a global resource update, so that when signal WE is set to 1, the local register 46 is loaded with the updated global resource. The innovative pre-charge circuit 21 schematically shown in Fig. 6 has been designed to maintain the desired exact and permanent correspondence between global resources and local resources, each time a global resource is updated. According to the present invention, as soon as a global resource is updated by the host computer/user, its value is loaded in the

corresponding local register in all the free neurons of the ANN.

Figs. 7A and 7B respectively show a more detailed construction of the pre-charge circuit of Fig. 6 when adapted to process the MaxIF and the global context.

Fig. 7A basically implements the flow chart of Fig. 4A in hardware. The architecture shown in FIG. 7A is derived from the partial architecture referenced 44 shown in Fig. 6 but is more particularly adapted to process the MaxIF. Turning to Fig. 7A, the partial architecture of the ANN now referenced 51 includes a few changes with respect to the Fig. 6 architecture to take into account the specificity of the AIF reduction process. In block 52, the pre-charge circuit 21 is the same and its output signal is ORed in a 2-way OR gate 53 with the signal which results of ANDing the CO and RA signals in 2-way AND gate 54.

As mentioned above, the CO signal is high when the neuron is engaged (committed) and the RA signal is high when the AIF reduction process is active. On the other hand, the data that can be stored in local register 55 is either the data present on the Data bus 13'or the distance stored in the Distance register 56 via multiplexor 57 (under neuron control logic supervision). Therefore, in this case, the WE signal which is output from OR gate 53 allows to store either data in the local AIF register 55.

Fig. 7B basically implements the flow chart of Fig. 4B in hardware. The architecture shown in FIG. 7B is derived from the partial architecture referenced 44 shown in Fig. 6 but is more particularly adapted to process the global context. Turning to Fig. 7B, the partial architecture of the ANN now referenced 58 includes a few changes with respect to the Fig. 6 architecture to take into account the specificity of a comparison which is required in this case. In block 59, the pre-charge circuit 21 is the same and its output signal WE is directly transmitted to the local register, in this case the context/norm (CXT)

register 60. The decoded signal that is output from Address decoder 49 is ANDed with the CO signal in 2-way AND gate 61 and the signal which is output therefrom controls a 1-bit register 62 which stores a"flag"to indicate if the neuron is "Selected"or not. The global resource present on Data bus 13' and the content of the CXT register 60 are compared in compare circuit 63. The result of the comparison (which depends upon there is a match or not) is stored as the flag bit in register 62. This flag bit is high thus only for engaged neurons when the Address is a global context address.

Fig. 8 is directly derived from the partial architectures referenced 51 and 58 shown in Figs. 7A and 7B respectively but is more particularly adapted to process both the MaxIF and the global context using a single pre-charge circuit. Now turning to Fig. 8, the partial architecture of the ANN now referenced 64 is provided with a block 65 which is characterized by a single address decoder circuit 66 that combines both decoder 49' (MaxIF address) and 49" (global context address)). In this case, two enable signals WE1 and WE2 are generated. This approach can be generalized to a plurality of global resource addresses.

While the invention has been particularly described with respect to a preferred embodiment thereof it should be understood by one skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.