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Title:
CIRCUITS WITH ENHANCED CURRENT PEAK TO VALLEY CURRENT RATIO
Document Type and Number:
WIPO Patent Application WO/2018/182709
Kind Code:
A1
Abstract:
Negative differential resistance (NDR) can be used in connection with memory circuits and/or devices. The performance of such a memory switch can be related to the peak to valley current ratio of the current through the memory switch. A higher current peak to valley current ratio can imply a more robust memory switch. In one embodiment, a circuit is described that generally operates by taking the output of a NDR exhibiting circuit including a resonant tunneling diode (RTD) and a first bipolar junction transistor (BJT) through a second BJT to generate current voltage characteristics having high current peak to valley current ratios; further the base current of the first BJT can be used to reduce the outputted valley current of the circuit.

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Inventors:
CHU-KUNG, Benjamin (2755 NW John Olsen Ave, Apt #F69Hillsboro, Oregon, 97124, US)
KUO, Charles C. (2501 NW 229th Ave, M/S RA3-252Hillsboro, Oregon, 97124, US)
DOYLE, Brian S. (11156 NW Montreux Lane, Portland, Oregon, 97229, US)
AUGUSTINE, Charles (16873 NW Lynch Lane, Portland, Oregon, 97229, US)
Application Number:
US2017/025486
Publication Date:
October 04, 2018
Filing Date:
March 31, 2017
Export Citation:
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Assignee:
INTEL CORPORATION (2200 Mission College Boulevard, Santa Clara, California, 95054, US)
International Classes:
H03K17/30; H03K17/74
Foreign References:
US5543748A1996-08-06
CN201398183Y2010-02-03
US20090294869A12009-12-03
US6184539B12001-02-06
US20090009218A12009-01-08
Attorney, Agent or Firm:
GRIFFIN, Malvern U. et al. (Eversheds Sutherland LLP, 999 Peachtree Street NESuite 230, Atlanta Georgia, 30309, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. A device, comprising:

a first bipolar junction transistor ("BJT") having a first emitter and an first collector;

a resonant tunneling diode (RTD) connected to the first emitter of the first BJT; and

a second BJT having a second base and a second collector, wherein the second base of the second BJT is connected to the first collector of the first BJT;

wherein the second BJT is configured to produce a current at the second collector when a first voltage is applied at the RTD.

2. The device of claim 1, wherein the first BJT and the second BJT form a complementary feedback pair.

3. The device of claim 1, wherein the first BJT comprises a pnp BJT.

4. The device of claim 2, wherein the second BJT comprises a npn BJT. 5. The device of claim 1, wherein the current produced at the second collector of the second BJT comprises an amplified first collector current of the first BJT.

6. The device of claim 1, wherein the first BJT has an emitter-base junction that is forward biased.

7. The device of claim 1 , wherein the first BJT has a collector-base junction that is forward biased.

8. The device of claim 1 , wherein the second BJT is configured to produce a current having a peak-to-parasitic current ratio that is indicative of a gain.

9. The device of claim 1 , wherein the second BJT is configured to produce a current having a negative differential resistance.

10. The device of claim 1 , wherein the second BJT is configured to produce a current having a peak-to-valley current ratio (PVCR) that is greater than about 150.

11. The device of claim 1 , wherein the second BJT is configured to produce a current having a PVCR that increases with increasing magnitude of current at a first base of the first BJT.

12. The device of claim 1 , wherein a second emitter of the second BJT is grounded.

13. The device of claim 1, wherein the first BJT includes a first base, the first base being configured to be biased from about 0 microamperes to about 700 microamperes.

14. The device of claim 1, wherein the device is configured to have a second voltage of about 0 volts to about 1.5 volts applied to the RTD diode connected to the first emitter of the first BJT. 15. The device of claim 1 , wherein the second collector of the second BJT is configured to be biased at about 0.23 volts.

16. A system comprising,

a device, the device comprising:

a first bipolar junction transistor ("BJT") having a first emitter and an first collector;

a resonant tunneling diode (RTD) connected to the first emitter of the first BJT; and

a second BJT having a second base and a second collector, wherein the second base of the second BJT is connected to the first collector of the first BJT; wherein the second BJT is configured to produce a current at the second collector when a first voltage within predetermined voltage range is applied at the RTD.

17. The system of claim 16, wherein the first BJT comprises a pnp BJT.

18. The system of claim 16, wherein the second BJT comprises a npn BJT.

19. The system of claim 16, wherein the current produced at the second collector of the second BJT comprises an amplified first collector current of the first BJT.

20. The system of claim 16, wherein the first BJT has an emitter-base junction that is forward biased.

21. The system of claim 16, wherein the first BJT has a collector-base junction that is forward biased. 22. The system of claim 16, wherein the second BJT is configured to produce a current having a peak-to-parasitic current ratio that is indicative of a gain.

23. The system of claim 16, wherein the second BJT is configured to produce a current having a negative differential resistance.

24. The system of claim 16, wherein the second BJT is configured to produce a current having a peak-to-valley current ratio (PVCR) that is greater than about 150.

25. The system of claim 16, wherein the second BJT is configured to produce a current having a PVCR that increases with increasing magnitude of current at a first base of the first BJT.

Description:
CIRCUITS WITH ENHANCED CURRENT PEAK TO VALLEY CURRENT RATIO

TECHNICAL FIELD

[0001] This disclosure generally relates to circuits with transistors.

BACKGROUND [0002] Negative differential resistance can refer to a property of an electrical circuit and/or device in which an increase in voltage across the electrical circuit and/or device terminals results in a decrease in electric current through the electrical circuit and/or device, for example, over a given voltage range. Negative differential resistance can be used in connection with memory circuits and/or devices. For example, two resistant tunneling diodes (RTDs) can be used to create a memory switch. The performance of such a memory switch can be related to the peak to valley current ratio of the current through the memory switch.

BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows a circuit diagram of a bipolar junction transistor (BJT) in series with a resistant tunneling diode (RTD).

[0005] FIG. 2 shows a plot that represents current voltage (IV) characteristic curves produced by the circuit diagram as shown and described in connection with FIG. 1, for different base currents at the base of the BJT of the circuit diagram of FIG. 1.

[0006] FIG. 3 shows a circuit diagram of an RTD in series with a first BJT connected with a second BJT in a complementary feedback pair (also referred to as a Sziklai pair) configuration, in accordance with one or more example embodiments of the disclosure.

[0007] FIG. 4 shows a plot of IV characteristic curves generated by the circuit diagram as shown and described in connection with FIG. 3 for different base currents at the base of the first BJT of the circuit diagram of FIG. 3, in accordance with one or more example embodiments of the disclosure.

[0008] FIG. 5 shows a diagram of an example flowchart for generating the circuit diagram described herein, in accordance with example embodiments of the disclosure. [0009] FIG. 6 shows a diagram of an example system, in accordance with example embodiments of the disclosure.

DETAILED DESCRIPTION

[0010] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout. [0011] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure. [0012] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0013] As mentioned, in various embodiments, negative differential resistance can be used in connection with memory circuits and/or devices. For example, two resistant tunneling diodes (RTDs) can be used to create a memory switch. The performance of such a memory switch can be related to the peak to valley current ratio of the current through the memory switch. In one embodiment, a higher current peak to valley current ratio can imply a more robust memory switch.

[0014] In one embodiment, a circuit is described that generally operates by taking the output of a NDR exhibiting circuit including a RTD and a first bipolar junction transistor (BJT) through a second BJT to generate IV characteristics having high current peak to valley current ratios; further the base current of the first BJT can be used to reduce the outputted valley current of the circuit. In one embodiment, the valley current represents the minimum current output from the circuit for a given base current at the base of the first BJT in the circuit over a predetermined voltage.

[0015] In particular, disclosed herein are systems, methods, and apparatus that describe a RTD connected in series with an emitter of a first BJT. Further, the systems, methods, and apparatus describe a current source can be connected to a base of the first BJT. In one embodiment, a voltage source can be connected to the RTD in series with the emitter of the first BJT. In another embodiment, a second BJT can be provided, the base of the second BJT being connected to a collector of the first BJT forming a complementary feedback pair (also referred to as a Sziklai pair); further the second BJT can produce a current at a collector of the second BJT in response to a predetermined voltage range applied at an emitter of the first BJT. [0016] In one embodiment, by sending the output of the first BJT through a second BJT, the collector current at the collector of the first BJT can serve as the base current at the base of the second BJT. Accordingly, only the collector current at the collector of the first BJT may be amplified by the second BJT. However, since the valley current including the first BJT in series with the RTD can be nearly zero, the valley current of the entire circuit (further including the second BJT) can be nearly zero as well. Consequently, the IV characteristic curves for the entire circuit can show an increased peak to valley current ratio.

[0017] In one embodiment, the BJTs can include heteroj unction bipolar transistors (HBTs). In another embodiment, HBTs can refer to a type of BJT that uses differing semiconductor materials for the emitter and base regions, thereby creating a heteroj unction. In one embodiment, by using BJTs and/or HBTs that include relatively small band gap materials (for example, InGaAs, GaAsSb, SiGe, Ge, InAs, GaSb), the power use of the BJTs and/or HBTs can be reduced. In one embodiment, using BJTs employing silicon, the peak voltage of circuit described herein may be about two volts. In another embodiment, using HBTs of appropriate materials (for example, InGaAs/InGaAs, InGaAs/GaAsSb, Si/SiGe, Si/SiGeC, InGaAs/InP, InAs/GaSb), the peak voltage of the circuit can be reduced to about 0.4 volts, thereby facilitating integration into electronic devices.

[0018] In another embodiment, for various applications, it may be desirable to have a memory switch having a current peak to valley current ratio of about 1,000. For example, Static Random Access Memory (SRAM) memory devices can have current on to off ratios approximately between 100,000 to approximately 1,000,000, or higher. In memory devices making use of negative differential resistance, peak to valley current ratios of 150 can be achieved. In one embodiment, the circuit described above and further shown in circuit diagram 300 and described in connection with FIG. 3 below can be placed in series with another, identical circuit, in order to create a memory cell exhibiting an NDR that is comparable to the NDR generated by SRAM memory.

[0019] In another embodiment, the circuit in circuit diagram 300 as shown and described in connection with FIG. 3 below can be used as an oscillator. This can be, for example, due to the fact that the circuit in circuit diagram 300, as shown and described in connection with FIG. 3, can exhibit high cutoff characteristics. For example, in the span of about a tenth of a volt, the current outputted from the circuit in circuit diagram 300 can decrease from almost a milliamp of current down to nearly zero amps of current, thereby facilitating the use of the circuit as an oscillator. [0020] In one embodiment, for typically memory applications, the memory may need to have a low voltage and a low power. In one embodiment, by using a high voltage device and use it while we can have very low current, the systems, methods, and apparatus can be used for memory applications. [0021] FIG. 1 shows a circuit diagram 100 of a BJT 102 in series with an RTD 104, in accordance with one or more example embodiments of the disclosure. In one embodiment, the RTD 104 can be fabricated using many different types of materials (such as III-V, type IV, II-VI semiconductor) and different types of resonant tunneling structures, such as the heavily doped p-n junction in Esaki diodes, double barrier, triple barrier, quantum well, or quantum wire. In one embodiment, the various layers comprising the RTD can be grown by molecular beam epitaxy, metal organic chemical vapor deposition (MOCVD), low- pressure chemical vapor deposition (LPCVD), and chemical vapor deposition (CVD). In another embodiment, GaAs and AlAs can be used to form this structure; alternatively or additionally, AlAs/InGaAs or InAlAs/InGaAs can be used in the RTD 104.

[0022] In one embodiment, the circuit diagram 100 can include a first BJT 102. In another embodiment, the BJT 102 can include an NPN BJT. In another embodiment, the BJT 102 can include a heteroj unction bipolar transistors (HBT). In another embodiment, HBTs can refer to a type of BJT that uses differing semiconductor materials for the emitter and base regions, thereby creating a heterojunction. In one embodiment, by using BJTs and/or HBTs that include relatively small band gap materials (for example, InGaAs, GaAsSb, SiGe, Ge, InAs, GaSb ), the power use of the BJTs and/or HBTs can be reduced.

[0023] In one embodiment, the RTD 104 can have IV characteristics (not shown) that exhibit a peak to valley current ratio of about 8. In one embodiment, the output of the RTD 104 can be placed through the first BJT 102, resulting in a circuit diagram 100 that can generate IV characteristic curves that exhibit a peak current that can be reduced by the base current of the first BJT 102. In another embodiment, the circuit diagram 100 can also generate IV characteristic curves exhibiting a valley current that can be reduced by the base current of the first BJT 102. [0024] In another embodiment, the circuit diagram 100 shows a connection 106 to a source voltage (not shown), for example, VDD. In one embodiment, the circuit diagram 100 shows a base 108 of the BJT 102. In another embodiment, the base 108 of the BJT 102 can be connected to a current source (not shown). In one embodiment, the circuit diagram 100 shows an emitter region 110 which can connect the BJT 102 to one side of the RTD 104. In another embodiment, the RTD 104 can be connected to ground 112. In one embodiment, the circuit diagram 100 shows a measurement point 106 in the circuit 100 where measurements can be made to generate the IV characteristic curves of the circuit diagram 200 as further shown and described in connection with FIG. 2 below. [0025] FIG. 2 shows a plot 200 that represents IV characteristic curves 207 produced by the circuit diagram 100 as shown and described in connection with FIG. 1, for different base currents at the base 108 of the BJT 102 of the circuit diagram 100, in accordance with one or more example embodiments of the disclosure.

[0026] In one embodiment, the plot 200 can include a y-axis 202 that represents the collector current at the collector 106 of the BJT 102 as shown and described in connection with FIG. 1. In one embodiment, the y-axis 202 can range from about 0 microamps to about 5 microamps. In one embodiment, the plot 200 can include an x-axis 204 that represents the collector voltage at the collector 106 of the BJT 102 as shown and described in connection with FIG. 1. In one embodiment, the x-axis 204 can range from about 0 volts to about 0.6 volts.

[0027] In one embodiment, the plot 200 shows a collection of peak currents 208 for the IV characteristic curves 207 measured at the collector 106 of the BJT 102, as shown and described in connection with FIG. 1. In one embodiment, the peak currents 208 represent the maximum current output from the circuit diagram 100 for a given base current at the base 108 of the BJT 102 of the circuit diagram 100, over the voltage range represented by the x-axis 204, that is, the collector voltage at the collector 106 of the BJT 102 of the circuit diagram 100.

[0028] In one embodiment, the plot 200 shows a collection of valley currents 210 for the IV characteristic curves 207 measured at the collector 106 of the BJT 102 as shown and described in connection with FIG. 1. In one embodiment, the valley currents 210 represent the minimum current output from the circuit diagram 100 for a given base current at the base 108 of the BJT 102 of the circuit diagram 100, over the voltage range represented by the x-axis 204, that is, the collector voltage at the collector 106 of the BJT 102 of the circuit diagram 100. [0029] In an embodiment, the arrow 218 of the plot 200 represents the effects of the base current at the base 108 of the BJT 102 of the circuit diagram 100 (as shown and described in connection with FIG. 1). In one embodiment, the arrow 218 of the plot 200 shows that the valley currents 210 can be reduced with increasing base current at the base 108 of the BJT 102 of the circuit diagram 100 for the IV characteristic curves 207 measured at the collector 106 of the BJT 102.

[0030] In one embodiment, the RTD 104 of the circuit diagram 100 (as shown and described in connection with FIG. 1) can have IV characteristics (not shown) that exhibit a peak to valley current ratio of about 8. In one embodiment, the output of the RTD 104 can be placed through a first BJT 102 (as shown and described in connection with FIG. 1), resulting in a circuit diagram 100 having IV characteristic curves 207 that exhibit peak currents 208 that can be reduced by the base current of the base 108 of the first BJT 102. In another embodiment, the circuit diagram 100 can also have IV characteristic curves 207 exhibiting valley currents 210 of the IV characteristic curves 207 that can be reduced by the base current of the base 108 of the first BJT 102. Accordingly, the effect of increasing the base current at the base 108 of the first BJT 102 on the valley currents 210 can be to reduce the valley currents 210 of the IV characteristic curves 207, as show and described by arrow 218 of FIG. 2 and related description. Additionally, the peak currents 208 of the IV characteristic curves 207 that represent the circuit diagram 100 can also decrease by about the same amount as the reduction in valley currents 210 with increasing base currents at the base 108 of the first BJT 102.

[0031] In one embodiment, the current output of the first BJT 102 of the circuit diagram 100 can generate IV characteristic curves (not shown) that have a nearly infinite peak to valley current ratio. That is, if the base current at the base 108 of the BJT 102 of the circuit diagram 100 is made equal to the corresponding valley current of the valley currents 210 for that particular base current, then the output of the first BJT 102 can be equal to the difference between the peak current exhibited by the circuit of circuit diagram 100 and the base current of the first BJT 102 divided by zero, which can yield a near infinite peak to valley current ratio.

[0032] In one embodiment, with one BJT (such as the first BJT 102), the valley current 210 of the IV characteristics of the circuit of circuit diagram 100 of FIG. l can be characterized as a parasitic current. In another embodiment, while the valley current (for example, a valley current of the valley currents 210 of the IV characteristics 207 of the circuit of circuit diagram 100 of FIG. l) can be reduced to nearly zero (for example, by increasing the base current at the base 108 of the first BJT 102), the parasitic current can effectively serve as the base current of the BJT 102. Accordingly, while the output of the first BJT 102, that is, the collector current at the collector 106 of the first BJT 102, shows a high peak to valley current ratio, the valley current 210 can be considered to have been transformed to a parasitic base current at the base 108 of the first BJT 102. Additionally, as mentioned, the peak currents 208 of the IV characteristic curves 207 that represent the circuit diagram 100 can also decrease by about the same amount as the reduction in valley currents 210 with increasing base currents at the base 108 of the first BJT 102.

[0033] FIG. 3 shows a circuit diagram 300 of an RTD 302 in series with a first BJT 304 connected with a second BJT 306 in a complementary feedback pair (also referred to as a Sziklai pair) configuration, in accordance with one or more example embodiments of the disclosure. In one embodiment, the circuit diagram 300 generally operates by taking the output of a NDR exhibiting circuit including a RTD 302 and a first BJT 304 (similar to the circuit diagram 100 of FIG. 1) through a second BJT 306 to generate IV characteristics having higher current peak to valley current ratios that the circuit including a RTD and a first BJT 304 (similar to the circuit diagram 100 of FIG. 1). Further, the base current of the first BJT 304 can be used to reduce the outputted valley current of the circuit 300. In one embodiment, the valley current represents the minimum current output from the circuit 300 for a given base current at the base of the first BJT 304 in the circuit 300 over a predetermined voltage.

[0034] In one embodiment, the output of the first BJT 304 can serve as the peak current served to the second BJT 306, and the valley current at the output of the first BJT 304 can be about zero. Further, the output current of the first BJT 304 can be amplified by the second BJT 306. However, since the valley current of the first BJT 304 can be close to zero, the valley current may not be amplified by the second BJT 306, thereby leading to high peak to valley current ratios for the circuit depicted in circuit diagram 300.

[0035] In one embodiment, the circuit diagram 300 includes an RTD 302. In one embodiment, the RTD 302 can be fabricated using many different types of materials (such as III-V, type IV, II-VI semiconductor) and different types of resonant tunneling structures, such as the heavily doped p-n junction in Esaki diodes, double barrier, triple barrier, quantum well, or quantum wire. In one embodiment, the various layers comprising the RTD 302 can be grown by molecular beam heteroepitaxy. In another embodiment, GaAs and AlAs can be used to form this structure; alternatively or additionally, AlAs/InGaAs or InAlAs/InGaAs can be used in the RTD 302.

[0036] In another embodiment, the circuit diagram 300 includes a first BJT 304. In one embodiment, the circuit diagram 300 includes a second BJT 306. In another embodiment, the first BJT 304 can include a PNP BJT. In another embodiment, the second BJT 306 can include a NPN BJT. [0037] In another embodiment, the first BJT 304 and/or second BJT 306 can include heteroj unction bipolar transistors (HBTs). In one embodiment, the BJTs can include heteroj unction bipolar transistors (HBTs). In another embodiment, HBTs can refer to a type of BJT that uses differing semiconductor materials for the emitter and base regions, thereby creating a heteroj unction. In one embodiment, by using BJTs and/or HBTs that include relatively small band gap materials (for example, InGaAs, GaAsSb, SiGe, Ge, InAs, GaSb), the power use of the BJTs and/or HBTs can be reduced. In one embodiment, using BJTs employing silicon, the peak voltage of circuit described herein may be about two volts. In another embodiment, using HBTs of appropriate materials (for example, InGaAs/InGaAs, InGaAs/GaAsSb, Si/SiGe, Si/SiGeC, InGaAs/InP, InAs/GaSb), the peak voltage of the circuit 300 can be reduced to about 0.4 volts, thereby facilitating integration into electronic devices.

[0038] In one embodiment, the circuit diagram 300 includes a connection 310 at one side of the RTD to a source voltage (not shown), for example, VDD. In one embodiment, the circuit diagram 300 shows a base 314 of a first BJT 304. In another embodiment, the base 314 of the first BJT 304 can be connected to a current source (not shown). [0039] In FIG. 3, the emitter voltage at the emitter 303 of the first BJT 304 can range from about 0 volts to about 1.5 volts in order for the circuit 300 to exhibit NDR, which can result from having the two BJTs (the first BJT 304 and the second BJT 306) in series in a Sziklai pair configuration. In one embodiment, the base current 314 at the base of the first BJT 304, can range from about 0 microamps to about 100 microamps.

[0040] In one embodiment, the collector 316 of the first BJT 304 can be connected to the base 318 of a second BJT 306. In one embodiment, the circuit diagram 300 shows that the emitter 319 of the second BJT 306 can be connected to ground 320. In one embodiment, the circuit diagram 300 shows a measurement point, that is, the collector 322 of the second BJT 306, in the circuit 300 where measurements can be made to generate the IV characteristics of the circuit diagram 300 as shown and described in connection with FIG. 4.

[0041] In one embodiment, by sending the current output of a first BJT 304 through a second BJT 306, the collector current at the collector 316 of the first BJT 304 can serve as the base current at the base 318 of the second BJT 306. Accordingly, only the collector current at the collector 316 of the first BJT 304 may be amplified by the second BJT 306. However, since the valley current generated by the portion of the circuit diagram 300 including the first BJT 304 in series with the RTD 302 (similar, but not necessarily identical to, the portion of circuit diagram 100 of FIG. 1) can be nearly zero (similar, but not necessarily identical to, the IV characteristic curves 207 of FIG. 2), the valley current of the entire circuit (further including the second BJT 306 as represented by circuit diagram 300) can be nearly zero as well. Consequently, the IV characteristic curves 407 shown and described in FIG. 4 below can be generated.

[0042] In one embodiment, the circuit in circuit diagram 300 as shown and described in connection with FIG. 3 can be placed in series with another, identical circuit, in order to create a memory cell exhibiting a latch IV comparable to the typical SRAM latch. In one embodiment, the circuit in circuit diagram 300 as shown and described in connection with FIG. 3 can be used as an oscillator. This can be, for example, due to the fact that the circuit in circuit diagram 300, as shown and described in connection with FIG. 3, can exhibit high cutoff characteristics. For example, in the span of about a tenth of a volt, the current outputted from the circuit in circuit diagram 300 can decrease from almost a milliamp of current down to nearly zero amps of current. In one embodiment, for typically memory application, the memory may need to have a low voltage and a low power. In one embodiment, by using a high voltage device and use it while we can have very low current, the systems, methods, and apparatus can be used for memory applications. [0043] FIG. 4 shows a plot 400 of IV characteristic curves 407 generated by the circuit diagram 300 as shown and described in connection with FIG. 3 for different base currents at the base 314 of the first BJT 304 of the circuit diagram 300 , in accordance with one or more example embodiments of the disclosure.

[0044] In one embodiment, the plot 400 shows a y-axis 402 that represents the current measured at the collector 322 of the second BJT 306 of circuit diagram 300 as shown and described in connection with FIG. 3. In one embodiment, the plot 400 shows an x-axis 404 that represents the voltage applied at the RTD 302 at the emitter 303 side of the first BJT 304 as shown and described in connection with FIG. 3. In one embodiment, the base current 314 at the base of the first BJT 304, can range from about 0 microamps to about 100 microamps. In one embodiment, the x-axis 404 shows the voltage from the emitter 303 of the first BJT 304 to the collector 322 of the second BJT 306. In one embodiment, the emitter voltage at the emitter 303 of the first BJT 304 can range from about 0 volts to about 1.5 volts in order for the circuit 300 to exhibit NDR, which can result from having the two BJTs (the first BJT 304 and the second BJT 306) in series in a Sziklai pair configuration.

[0045] In one embodiment, the plot 400 shows peak currents 408 of the IV characteristic curves 407 of the circuit diagram 300 as shown and described in connection with FIG. 3. In one embodiment, the peak currents can be measured at the collector 322 of the second BJT 306 shown and described in connection with FIG. 3. In one embodiment, the peak currents 408 represent the maximum current output from the circuit diagram 300 of FIG. 3 for different base currents at the base 314 of the first BJT 304 of the circuit diagram 300, over the voltage range represented by the x-axis 404, that is, voltage applied at the RTD 302 at the emitter 303 side of the first BJT 304 of the circuit diagram 300.

[0046] In one embodiment, plot 400 shows the valley currents 410 of the IV characteristics of the circuit diagram as shown and described in connection with FIG. 3. In one embodiment, the valley currents 410 represent the measurements made at the collector 322 of the second BJT 306 as shown and described in connection with FIG. 3. In one embodiment, the valley currents 410 represent the minimum current output from the circuit diagram 300 of FIG. 3 for a given base current at the base 314 of the first BJT 304 of the circuit diagram 300, over the voltage range represented by the x-axis 404, that is, voltage applied at the RTD 302 at the emitter 303 side of the first BJT 304 of the circuit diagram 300.

[0047] In one embodiment, plot 400 shows an arrow 414 that represents the effect of increasing the base current at the base 314 of the first BJT 304 in circuit diagram 300 as shown and described in connection with FIG. 3. In one embodiment, the arrow 414 of the plot 400 shows that the valley currents 410 can be reduced with increasing base current at the base 314 of the first BJT 304 in circuit diagram 300 for the IV characteristic curves 408 as measured at the collector 322 of the second BJT 306 as shown and described in connection with FIG. 3. [0048] In one embodiment, for zero base current, that right most curve shows a valley current of about 0.6 milliamps, which can serve as a parasitic current.

[0049] In one embodiment, since the plot 400 shows the collector current at the collector 322 of the second BJT 306, the base current at the base 318 of the second BJT 306 is not shown, and therefore, the parasitic base current is not shown in plot 400. Nevertheless, in one embodiment, as the base current at the base 318 of the second transistor 306 increases, that base current can be effectively subtracted from the outputted valley currents 410 of the IV characteristic curves 407.

[0050] In one embodiment, having the first BJT 304 in series with the RTD 302 allows for a PVCR increase because the valley current can be decreased by the base current of the base 314 of the first BJT 304; however, the peak current 408 to parasitic current (not shown) can remain the same. In one embodiment, by adding a second BJT such as the second BJT 306 shown and described in connection with FIG. 3, the peak current 408 can be increased without increasing the parasitic current (not shown) of the first BJT 304.

[0051] In one embodiment, a relatively high collector current can be generated at the collector 316 of the first BJT 304 but the high collector current at the collector 316 of the first BJT 304 can serve as the valley current from the first BJT 304, which may not be amplified by the second BJT 306. Accordingly, in terms of the peak to parasitic ratio for the current produced by the circuit 300 of FIG. 3, the peak current of the first BJT 304 multiplied by the amplification of the second BJT 306; however, the parasitic current can be the base current at the base 318 of the second BJT, thereby permitting a very high peak to parasitic ratio.

[0052] FIG. 5 shows a diagram of an example flowchart for generating the circuit diagram described herein, in accordance with example embodiments of the disclosure. In block 502, a first BJT having a first emitter and a first collector and a RTD connected to the first emitter of the first BJT can be provided. In one embodiment, the RTD can be fabricated using many different types of materials (such as III-V, type IV, II-VI semiconductor) and different types of resonant tunneling structures, such as the heavily doped p-n junction in Esaki diodes, double barrier, triple barrier, quantum well, or quantum wire. In one embodiment, the various layers comprising the RTD can be grown by molecular beam epitaxy, MOCVD, LPCVD, and CVD. In another embodiment, GaAs and AlAs can be used to form this structure; alternatively or additionally, AlAs/InGaAs or InAlAs/InGaAs can be used in the RTD.

[0053] In another embodiment, the first BJT can include a PNP BJT. In another embodiment, the first BJT can include heteroj unction bipolar transistors (HBTs). In one embodiment, the BJTs can include heteroj unction bipolar transistors (HBTs). In another embodiment, HBTs can refer to a type of BJT that uses differing semiconductor materials for the emitter and base regions, thereby creating a heteroj unction. In one embodiment, by using BJTs and/or HBTs that include relatively small band gap materials (for example, InGaAs, GaAsSb, SiGe, Ge, InAs, and GaSb), the power use of the BJTs and/or HBTs can be reduced. In one embodiment, using BJTs employing silicon, the peak voltage of circuit described herein may be about two volts. In another embodiment, using HBTs of appropriate materials (for example, InGaAs/InGaAs, InGaAs/GaAsSb, Si/SiGe, Si/SiGeC, InGaAs/InP, InAs/GaSb ), the peak voltage of the circuit can be reduced to about 0.4 volts, thereby facilitating integration into electronic devices. [0054] In block 504, a second BJT having a second base and a second collector can be provided; the second base of the second BJT can be connected to the first collector of the first BJT; further, the second BJT can be configured to produce a current at the second collector when a first voltage is applied at the RTD. In one embodiment, by sending the current output of a first BJT through a second BJT, the collector current at the collector of the first BJT can serve as the base current at the base of the second BJT. Accordingly, only the collector current at the collector of the first BJT may be amplified by the second BJT. However, since the valley current generated by the portion of the circuit diagram including the first BJT in series with the RTD can be nearly zero (similar, but not necessarily identical to, the IV characteristic curves 207 of FIG. 2), the valley current of the entire circuit (further including the second BJT 306 as represented by circuit diagram 300 of FIG. 3) can be nearly zero as well. Consequently, the IV characteristic curves 407 shown and described in FIG. 4 below can be generated.

[0055] In block 506, a current source can be connected to a base of the first BJT. In one embodiment, the base current at the base of the first BJT, can range from about 0 microamps to about 100 microamps. [0056] In block 508, a voltage source can be connected to the resonant tunneling diode (RTD) in series with the emitter of the first BJT. In one embodiment, the emitter voltage at the emitter of the first BJT can range from about 0 volts to about 1.5 volts, for example, in order for the circuit to exhibit NDR, which can result from having a RTD connected in series with the two BJTs (the first BJT and the second BJT) in a Sziklai pair configuration. [0057] In one embodiment, the circuit in circuit diagram as shown and described in connection with FIG. 3 can be placed in series with another, identical circuit, in order to create a memory cell exhibiting a latch IV comparable to the typical SRAM latch. In one embodiment, the circuit in circuit diagram 300 as shown and described in connection with FIG. 3 can be used as an oscillator. This can be, for example, due to the fact that the circuit in circuit diagram 300, as shown and described in connection with FIG. 3, can exhibit high cutoff characteristics. For example, in the span of about a tenth of a volt, the current outputted from the circuit in circuit diagram 300 can decrease from almost a milliamp of current down to nearly zero amps of current. In one embodiment, for typically memory application, the memory may need to have a low voltage and a low power. In one embodiment, by using a high voltage device and use it while we can have very low current, the systems, methods, and apparatus can be used for memory applications. [0058] FIG. 6 depicts an example of a system 600 according to one or more embodiments of the disclosure. In one embodiment, the circuits described herein can be used in connection with or as a part of any of the elements and/or components of system 600. In one embodiment, system 600 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 600 can include a system on a chip (SOC) system.

[0059] In one embodiment, system 600 includes multiple processors including processor 610 and processor N 605, where processor N 605 has logic similar or identical to the logic of processor 610. In one embodiment, processor 610 has one or more processing cores (represented here by processing core 1 612 and processing core N 612N, where 612N represents the Nth processor core inside processor 610, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 6). In some embodiments, processing core 612 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 610 has a cache memory 616 to cache instructions and/or data for system 600. Cache memory 616 may be organized into a hierarchical structure including one or more levels of cache memory.

[0060] In some embodiments, processor 610 includes a memory controller (MC) 614, which is configured to perform functions that enable the processor 610 to access and communicate with memory 630 that includes a volatile memory 632 and/or a non-volatile memory 634. In some embodiments, processor 610 can be coupled with memory 630 and chipset 620. Processor 610 may also be coupled to a wireless antenna 678 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna 678 operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. [0061] In some embodiments, volatile memory 632 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 634 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0062] Memory device 630 stores information and instructions to be executed by processor 610. In one embodiment, memory 630 may also store temporary variables or other intermediate information while processor 610 is executing instructions. In the illustrated embodiment, chipset 620 connects with processor 610 via Point-to-Point (PtP or P-P) interface 617 and P-P interface 622. Chipset 620 enables processor 610 to connect to other elements in system 600. In some embodiments of the disclosure, P-P interface 617 and P-P interface 622 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used. [0063] In some embodiments, chipset 620 can be configured to communicate with processor 610, the processor N 605, display device 640, and other devices 672, 676, 674, 660, 662, 664, 666, 677, etc. Chipset 620 may also be coupled to the wireless antenna 678 to communicate with any device configured to transmit and/or receive wireless signals.

[0064] Chipset 620 connects to display device 640 via interface 626. Display 640 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 610 and chipset 620 are integrated into a single SOC. In addition, chipset 620 connects to bus 650 and/or bus 655 that interconnect various elements 674, 660, 662, 664, and 666. Bus 650 and bus 655 may be interconnected via a bus bridge 672. In one embodiment, chipset 620 couples with a non-volatile memory 660, a mass storage device(s) 662, a keyboard/mouse 664, and a network interface 666 via interface 624 and/or 604, smart TV 676, consumer electronics 677, etc.

[0065] In one embodiment, mass storage device(s) 662 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 666 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0066] While the modules shown in FIG. 6 are depicted as separate blocks within the system 600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 616 is depicted as a separate block within processor 610, cache memory 616 or selected elements thereof can be incorporated into processor core 612.

[0067] It is noted that the system 600 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor packages (for example, the semiconductor packages described in connection with any of FIGS. 1-6), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0068] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0069] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0070] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data. [0071] Example 1 is a device, comprising a first bipolar junction transistor ("BJT") having a first emitter and an first collector; a resonant tunneling diode (RTD) connected in series with the first emitter of the first BJT; and a second BJT having a second base and a second collector, wherein the second base of the second BJT is connected to the first collector of the first BJT; wherein the second BJT is configured to produce a current at the second collector when a first voltage within predetermined voltage range is applied at the RTD. In example 2, the device of example 1 can optionally include the first BJT and the second BJT forming a complementary feedback pair. In example 3, the device of any one of examples 1 or 2 can optionally include the first BJT which comprises a pnp BJT. In example 4, the device of any one of examples 1-3 can optionally include the second BJT which comprises a npn BJT. In example 5, the device of any one of examples 1-4 can optionally include current produced at the second collector of the second BJT comprising an amplified first collector current of the first BJT. In example 6, the device of any one of examples 1-5 can optionally include a first BJT with an emitter-base junction being forward biased. In example 7, the device of any one of examples 1-6 can optionally include a first BJT with a collector-base junction being forward biased. In example 8, the device of any one of examples 1-7 can optionally include current produced by the second BJT exhibiting a peak-to-parasitic current ratio that is indicative of a gain. In example 9, the device of any one of examples 1-8 can optionally include current produced by the second BJT exhibiting a negative differential resistance. In example 10, the device of any one of examples 1-9 can optionally include current produced by the second BJT that exhibiting a peak-to-valley current ratio (PVCR) that is greater than about 150. In example 11, the device of any one of examples 1-10 can optionally include current produced by the second BJT exhibiting a PVCR that increases with increasing magnitude of current at a first base of the first BJT. In example 12, the device of any one of examples 1-11 can optionally include a second emitter of the second BJT being grounded. In example 13, the device of any one of examples 1-12 can optionally include the first BJT, which includes a first base, the first base being biased from about 0 microamperes to about 700 microampere. In example 14, the device of any one of examples 1-13 can optionally include a second voltage of about 0 volts to about 1.5 volts which being applied to the RTD diode in series with the first emitter of the first BJT. In example 15, the device of any one of examples 1-14 can optionally include the second collector of the second BJT being biased at about 0.23 volts. [0072] Example 16 is a system, comprising a device, the device comprising: a first bipolar junction transistor ("BJT") having a first emitter and an first collector; a resonant tunneling diode (RTD) connected in series with the first emitter of the first BJT; and a second BJT having a second base and a second collector, wherein the second base of the second BJT is connected to the first collector of the first BJT; wherein the second BJT is configured to produce a current at the second collector when a first voltage within predetermined voltage range is applied at the RTD. In example 17, the system of example 16 can optionally include the first BJT and the second BJT forming a complementary feedback pair. In example 18, the system of any one of examples 16 or 17 can optionally include the first BJT which comprises a pnp BJT. In example 19, the system of any one of examples 16-18 can optionally include the second BJT which comprises a npn BJT. In example 20, the system of any one of examples 16-19 can optionally include current produced at the second collector of the second BJT comprising an amplified first collector current of the first BJT. In example 21, the system of any one of examples 16-20 can optionally include a first BJT with an emitter-base junction being forward biased. In example 22, the system of any one of examples 16-21 can optionally include a first BJT with a collector-base junction being forward biased. In example 23, the system of any one of examples 16-22 can optionally include current produced by the second BJT exhibiting a peak-to-parasitic current ratio that is indicative of a gain. In example 24, the system of any one of examples 16-23 can optionally include current produced by the second BJT exhibiting a negative differential resistance. In example 25, the system of any one of examples 16-24 can optionally include current produced by the second BJT that exhibiting a peak-to-valley current ratio (PVCR) that is greater than about 150. In example 26, the system of any one of examples 16-25 can optionally include current produced by the second BJT exhibiting a PVCR that increases with increasing magnitude of current at a first base of the first BJT. In example 27, the system of any one of examples 16-26 can optionally include a second emitter of the second BJT being grounded. In example 28, the system of any one of examples 16-27 can optionally include the first BJT, which includes a first base, the first base being biased from about 0 microamperes to about 700 microampere. In example 29, the system of any one of examples 16-28 can optionally include a second voltage of about 0 volts to about 1.5 volts which being applied to the RTD diode in series with the first emitter of the first BJT. In example 30, the system of any one of examples 16-29 can optionally include the second collector of the second BJT being biased at about 0.23 volts.

[0073] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

[0074] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[0075] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense. [0076] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and performing any incorporated methods and processes. The patentable scope of certain embodiments of the invention is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.