CLOCK CALIBRATION CIRCUIT

WIPO Patent Application WO/2022/111340

A1

A clock calibration circuit (200), comprising: a clock generation module (20), a clock frequency division module (30), and a modem (40) which are connected to each other. When the modem (40) is switched to a sleep mode, the modem (40) outputs a generated sleep mode indication signal to the clock generation module (20), and outputs a generated first control signal to the clock frequency division module (30); in response to the sleep mode indication signal, the clock generation module (20) switches to a sleep mode, and outputs a generated first clock signal in the sleep mode to the clock frequency division module (30); in response to the first control signal, the clock frequency division module (30) performs frequency division on the first clock signal in the sleep mode on the basis of configuration parameters corresponding to the sleep mode, generates a second clock signal in the sleep mode, and outputs the second clock signal to the modem (40); when the modem (40) is switched to a working mode, the modem (40) calibrates a system clock signal on the basis of the second clock signal in the sleep mode. Therefore, calibration of a system clock can be realized, calibration efficiency can be effectively improved, and system power consumption can also be reduced.

JP3425876	PULSE GENERATING CIRCUIT
JP6815565	Phase amplitude control oscillator

YAN LONG (CN)
TANG BO (CN)
ZOU XU (CN)

PCT/CN2021/131026

June 02, 2022

November 16, 2021

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UNISOC CHONGQING TECH CO LTD (CN)

H03L7/24

WO2004095692A2

2004-11-04

CN205179018U	2016-04-20
CN101252720A	2008-08-27
CN112422126A	2021-02-26
CN101662823A	2010-03-03
CN102522985A	2012-06-27

SCIHEAD IP LAW FIRM (CN)

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