Title:
CLOCK DATA RECOVERY APPARATUS, OPTICAL MODULE AND OPTICAL LINE TERMINAL
Document Type and Number:
WIPO Patent Application WO/2019/210473
Kind Code:
A1
Abstract:
Provided are a clock data recovery apparatus, an optical line terminal and a passive optical communication system. The clock data recovery apparatus comprises: a phase detection loop unit, a frequency oscillation unit, a frequency detection loop unit and a data acquisition unit. The frequency detection loop unit is used to, when there is no data stream signal input to the clock data recovery apparatus, determine a first frequency difference between a reference clock signal and a signal output by the frequency oscillation unit, and convert the first frequency difference into a first voltage signal. The frequency oscillation unit is used to oscillate the first voltage signal, and output a signal obtained by oscillating the first voltage signal. The phase detection loop unit is used to, when there is a data stream signal input to the clock data recovery apparatus, determine a phase difference between the data stream signal and the signal output by the frequency oscillation unit, and convert the phase difference into a second voltage signal. The frequency oscillation unit is further used to oscillate the second voltage signal, and output a signal obtained by oscillating the second voltage signal. By means of the clock data recovery apparatus, the optical line terminal and the passive optical communication system provided in the present application, a clock data recovery technique can be realized.
Inventors:
ZHENG JIANYU (CN)
LI SHENGPING (CN)
YU CHANGLIANG (CN)
YE ZHICHENG (CN)
LI SHENGPING (CN)
YU CHANGLIANG (CN)
YE ZHICHENG (CN)
Application Number:
PCT/CN2018/085400
Publication Date:
November 07, 2019
Filing Date:
May 03, 2018
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H03L7/06
Foreign References:
| CN104205719A | 2014-12-10 | |||
| CN102611440A | 2012-07-25 | |||
| CN201113978Y | 2008-09-10 | |||
| US7359474B2 | 2008-04-15 |
Other References:
ZHANG, AIQIN: "Research and Design of High Speed Clock Recovery Circuit on ASIC", CHINA MASTER S THESES FULL-TEXT DATABASE, 15 December 2011 (2011-12-15), pages 1 - 74, XP055753344
See also references of EP 3783803A4
See also references of EP 3783803A4
Attorney, Agent or Firm:
LONGSUN LEAD IP LTD. (CN)
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