CLOCK AND DATA RECOVERY FOR BURST-MODE SERIAL SIGNALS

WIPO Patent Application WO/2011/088369

A3

A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

WO/1999/046886	OFF-LINE BROADBAND NETWORK INTERFACE
JP3212385	CLOCK RECOVERY CIRCUIT
JPH11122232	PHASE DETECTION CIRCUIT AND TIMING EXTRACT CIRCUIT USING THE PHASE DETECTION CIRCUIT

KYLES IAN (US)
PAHOMSKY EUGENE (US)

PCT/US2011/021367

November 24, 2011

January 14, 2011

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VITESSE SEMICONDUCTOR CORP (US)
KYLES IAN (US)
PAHOMSKY EUGENE (US)

H04L7/027; H03K7/00

US20090327788A1	2009-12-31
US20050091559A1	2005-04-28
US20060125665A1	2006-06-15
US20080056420A1	2008-03-06

CAVANAGH, Daniel M. et al. (O'Neill & Singh LLP,18200 Von Karman Ave.,Suite 72, Irvine California, US)

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