Title:
CLOCK DATA RECOVERY CIRCUIT AND CLOCK DATA RECOVERY METHOD
Document Type and Number:
WIPO Patent Application WO/2022/183774
Kind Code:
A1
Abstract:
A clock data recovery circuit and a clock data recovery method. The clock data recovery circuit comprises a time delay loop (100), a frequency locking loop (200) and a deserializer (300), wherein the time delay loop (100) is configured to delay input data according to a phase of a clock signal, so as to realize phase alignment; the frequency locking loop (200) is connected to the time delay loop (100), and is configured to adjust the frequency of the clock signal according to the delayed input data, so that the frequency of the clock signal is consistent with the frequency of the input data; and the deserializer (300) is respectively connected to the time delay loop (100) and the frequency locking loop (200), and is configured to deserialize the input data according to the clock signal.
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Inventors:
PAN QUAN (CN)
XIAO WENBO (CN)
HUANG QIWEI (CN)
YANG JUNYI (CN)
DING XUEWEI (CN)
HAO YINGLI (CN)
XIAO WENBO (CN)
HUANG QIWEI (CN)
YANG JUNYI (CN)
DING XUEWEI (CN)
HAO YINGLI (CN)
Application Number:
PCT/CN2021/130752
Publication Date:
September 09, 2022
Filing Date:
November 15, 2021
Export Citation:
Assignee:
ZTE CORP (CN)
UNIV SOUTHERN SCI & TECH (CN)
UNIV SOUTHERN SCI & TECH (CN)
International Classes:
H03L7/18
Foreign References:
| CN1666456A | 2005-09-07 | |||
| CN101657966A | 2010-02-24 | |||
| US20040196106A1 | 2004-10-07 |
Attorney, Agent or Firm:
JIAQUAN IP LAW (CN)
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