Title:
CLOCK DATA RECOVERY CIRCUIT AND WIRELESS MODULE INCLUDING SAME
Document Type and Number:
WIPO Patent Application WO/2012/111133
Kind Code:
A1
Abstract:
This clock data recovery circuit (11) is provided with: a ring oscillator (17); an oscillation control circuit unit (15) which starts and stops operation of the ring oscillator (17) depending upon the presence or absence of input of a PWM signal; a counter circuit unit (19) for counting pulse signals and holding an N-bit count value; a register circuit unit (21) which has an M-bit register and is configured so as to be able to transfer the upper M bits among the N-bit count value as a reference count value in response to the input of a transfer signal; a comparator circuit unit (25) which outputs a timing clock if the count number held by the counter circuit unit (19) exceeds the reference count value held by the register circuit unit (21); and a transfer control circuit unit (23) which, in synchronization with the start-up timing of the PWM signal, generates the transfer signal for transferring the reference count value from the counter circuit unit (19) to the register circuit unit (21) and a reset signal for resetting the counter circuit unit (19).
Inventors:
SANO EIICHI
AMEMIYA YOSHIHITO
AMEMIYA YOSHIHITO
Application Number:
PCT/JP2011/053416
Publication Date:
August 23, 2012
Filing Date:
February 17, 2011
Export Citation:
Assignee:
UNIV HOKKAIDO NAT UNIV CORP (JP)
SANO EIICHI
AMEMIYA YOSHIHITO
SANO EIICHI
AMEMIYA YOSHIHITO
International Classes:
H04L25/49; H04L7/027
Foreign References:
| JPS6172454A | 1986-04-14 |
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
Yoshiki Hasegawa (JP)
Yoshiki Hasegawa (JP)
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Claims: