TECHNICAL FIELD The present invention relates to an apparatus and method for recovering clock and data from an M-level signal of a receiver in a transmission system such as - but not limited to - a fiber optical transmission system with direct detection optical receivers.

BACKGROUND In optical communications, intensity modulation (IM) is a form of modulation, in which the optical power output of a source is varied in accordance with some characteristic of the modulation signal. The envelope of the modulated optical signal corresponds to the modulating signal in the sense that the instantaneous power of the envelope is an envelope of the characteristic of interest in the modulation signal. Recovery of the modulating signal is usually achieved by direct detection (DD) through a photo-detector.

Next-generation ultra-high-speed short-reach optical fiber links will utilize small, cheap and low power consumption transceivers. All those requirements are mainly imposed due to the limited space of data center equipment. The transceivers shall support intra- and inter-data center connections from a few hundred meters up to several tens of kilometers, respectively. Data centers are facilities that store and distribute the data on the Internet. With an estimated number of more than 100 billion of web pages on over 100 million websites, it is clear that those data centers shall be adapted to contain a huge amount of data. With almost two billion users accessing all these websites, including a growing amount of high bandwidth video, it is hard to comprehend how much data is being uploaded and downloaded every second on the Internet. A data center, as defined in the ANSI/TIA EIA-942 standard "Telecommunications Infrastructure Standard for Data Centers", is a building or portion of a building whose primary function is to house a computer room and its support areas. The main functions of a data center are to centralize and consolidate information technology (IT) resources, house network operations, facilitate e-business and to provide uninterrupted service to mission- critical data processing operations. Data centers can be part of an enterprise network, a commercial venture that offers to host services for others or a co-location facility where users can place their own equipment and connect to the service providers over the building's connections. Data centers may serve local area networks (LANs) or wide area networks (WAN) and may be comprised of switches connecting user devices to server devices and other switches connecting server devices to storage devices.

A preferred solution may be to transmit 100 Gbit/s per wavelength, which is very challenging when a very cheap solution is required. A coherent approach is out of scope as it requires high power and expensive devices. Therefore, IM and DD schemes are preferred. The mature on-off keying modulation format, widely used in non-coherent systems, has been also investigated for so-called 100-G applications at 100 Gbit/s per wavelength speed. However, such a solution would require expensive high-bandwidth optics and electronics. To overcome that drawback, advanced modulation formats supported by digital signal processing (DSP) have been investigated as an alternative technology to support 100-G applications, the most promising candidates being duo-binary 4-level pulse amplitude modulation (DB-PAM-4), discrete multi-tone modulation (DMT) and carrier-less amplitude and phase modulation (CAP). All the aforementioned approaches require either expensive components or enhanced DSP or both of them and cannot be considered as serious candidates for data center connections.

As a DSP has to be avoided, simple analog equalization schemes included in a clock data recovery (CDR) block are needed. DMT and CAP require transmitter and receiver DSP blocks and are not considered seriously for cheap transceivers. Then, the PAM-4 format is remaining as one option since a transmitter (Tx) does not require a digital-to-analog converter (DAC). Also, at the receiver side, a high resolution analog-to-digital converter (ADC) is not necessary if the transmission systems can be designed to provide an acceptable bit error rate (BER) for a forward error correction (FEC) block.

Fig. 1 shows a schematic block diagram of a conventional IM/DD-based PAM-4 transmission system 100. A transmission PAM-4 signal (Tx PAM-4) is FEC encoded by an encoder (Tx FEC) and equalized by an equalizer (Tx EQ) at the transmitter side, for example, by using a simple analog equalizer (pre-emphases), amplified by a modulator driver (MD) and converted in the optical domain by a modulator (MOD) and a local oscillator laser (LO). The obtained optical signal is transmitted over a multimode fiber (MMF) or a single mode fiber (SMF) and detected by using a photo-diode (PD). The obtained electrical signal is equalized (Rx EQ), for example, by a continuous-time linear equalizer (CTLE) or a multi-tap finite impulse response filter (FIR). A subsequent clock recovery (CR) block uses signals before and after a 2-bit ADC to extract clock from the received signal. After a FEC decoder (Rx FEC), the BER of an obtained PAM-4 signal (Rx PAM-4) at the receiver output should be below some predefined threshold. The architecture of Fig. 1 is a simple and cheap solution for an optical transmission system. All blocks can operate at high speed and the clock recovery (CR) block can be kept simple. However, due to bandwidth limitations of electrical circuits, it is not a preferred solution to work with analog values and at frequencies higher than the symbol rate. So far, in PAM-4 systems for example, the CR block based on two samples per symbols is implemented. In on-off keying (OOK) systems, a preferable CR block was based on an Alexander nonlinear phase detector using two samples per symbol and a specific logic to derive clock. This phase detector uses three samples A, B and C at 2fs frequency, where fs corresponds to the symbol rate and verifies fs=1/UI where Ul corresponds to a unit interval (i.e., the time period T), and makes a decision whether the clock is early or late. Phase detector outputs can be expressed as "0", and "+" (which can mean "early", "ambiguous", and "late",

respectively). The signs of samples can be expressed as "-" and "+", while "+/-" means that this sample is irrelevant if other conditions are fulfilled.

Linear and nonlinear phase detectors using two samples per symbol are known, which are often used in practical PAM-4 systems. The linear variant deals with analog and digital signals, selects "good transitions" and has very good jitter performance, but the main problem comes from oversampling and handling analog values. The nonlinear variant is based on selective transitions of an Alexander phase detector. This variant introduces more jitter, but the implementation is not difficult at medium symbol rates. A disadvantage of those two variants is oversampling, which presents a big problem at high data speeds, for example, at 56G, for which a 1 12G clock is required. Some solutions based on a single sample per symbol suffer either from the fact that they require analog signal processing or there are problems related to timing error detector characteristic (TEDC) such as asymmetric shape or large hang-up range. It should be noted that, in general for well-designed phase detectors, two samples per symbol are always better than one sample per symbol. In the ideal case (i.e., when there is no implementation constraint), analog phase detectors are also better than digital (quantized) phase detectors.

An eye diagram is a common indicator of the quality of signals in high-speed digital transmissions. An oscilloscope generates an eye diagram by overlaying sweeps of different segments of a long data stream driven by a master clock. Overlaying many bits produces an eye diagram, so called because the resulting image looks like the opening of an eye. In an ideal world, eye diagrams would look like rectangular boxes. In reality, communications are imperfect, so that the transitions do not line perfectly on top of each other, which results in an eye-shaped pattern. Differences in timing and amplitude from bit to bit cause the eye opening to shrink. Fig. 2 shows a time diagram with a schematic eye diagram of a received signal with different sampling phases in the case of an early sampling. More specifically, Fig. 2 depicts an example of an early sampling phase with samples A, B, and C and a best sampling phase (BSP) at the highest opening of an eye diagram, where the sample C is shortly before the best sampling phase. The Alexander phase detector uses only the signs of three samples and drives an oscillator.

A truth table is a mathematical table used in logic - specifically in connection with Boolean algebra, Boolean functions, and propositional calculus - to compute the functional values of logical expressions on each of their functional arguments, that is, on each combination of values taken by their logical variables. Practically, a truth table is composed of one column for each input variable, and one final column for all of the possible results of the logical operation that the table is meant to represent. Each row of the truth table therefore contains one possible configuration of the input variables and the result of the operation for those values. Fig. 3 shows a truth table of an Alexander phase detector, wherein the respective signs: Sign(A), Sign(B) and Sign(C) of the samples A, B and C of Fig. 2 with respect to the best sampling phase are used as input variables of the truth table to derive output values -1 , 0, and +1 for controlling the oscillator. The values "0" and "+" can be interpreted in the sense of "early", "ambiguous" and "late", respectively. However, as already mentioned above, this phase detector is disadvantageous due to oversampling and high jitter in PAM-4 systems.

SUMMARY

It is therefore an object of the present invention to provide a clock and data recovery apparatus and method, by means of which clock and data recovery can be further simplified and sampling speed can be lowered.

The object is achieved by the features of the independent claims. Further embodiments of the invention are apparent from the dependent claims, the description and the figures.

According to a first aspect, the invention relates to an apparatus for recovering clock and data from an M-level signal of a receiver in a transmission system, where M is a positive integer and a power of two, and wherein two consecutive analog data of the M-level signal are sampled at a distance of one symbol period with respect to each other. The apparatus comprises an M-level log2(M)-bit analog-to-digital converter (ADC) connected at an input of the apparatus, the M-level log2(M)-bit ADC being adapted to output an outer level bit corresponding to a polarity of an amplitude difference between an analog data of the M-level signal and a closest voltage threshold amongst 2-M and M-2 and adapted to output the most significant bit corresponding to a polarity of an amplitude difference between the analog data of the M-level signal and a voltage threshold equal to zero; a first voltage comparator connected at the input of the apparatus, the first voltage comparator being adapted to compare a first amplitude difference corresponding to an amplitude difference between the analog data and a first controllable threshold value; a second voltage comparator connected at the input of the apparatus, the second comparator being adapted to compare a second amplitude difference corresponding to an amplitude difference between the analog data and a second controllable threshold value; and a three-valued logic unit adapted to output, through a truth table, a truth value amongst -1 , 0 and +1 , based on a polarity of the most significant bit, a polarity of the outer level bit and a polarity of an amplitude difference to be selected amongst the first and second amplitude differences. Thereby, the proposed clock and data recovery (CDR) apparatus can be advantageously used in transmission systems with M-level signals (e.g., PAM-4 or PAM-8 or other multi-level transmission systems). Indeed, clock extraction at very high baud (Bd) rates can be carried out since the proposed CDR apparatus uses only one sample per symbol. The proposed CDR apparatus is also easy to implement as it requires only digital circuits and does not deal with analog values. Furthermore, the proposed CDR apparatus can control the sampling phase by adjusting the phase detector thresholds. In addition, it can enable timing in highspeed systems, in which the clear multi-level (e.g., PAM-4 or PAM-8) signal is available before clock and data recovery, by using high bandwidth components and systems that do not require an enhanced DSP after the ADC block, which is the main target for small-size and low-power consumption transceivers.

According to a first implementation of the apparatus according to the first aspect, the M-level signal has M equidistant levels, the M levels being odd integers starting from ±1 , and the analog data has an amplitude outside the range from 2-M to M-2.

According to a second implementation of the apparatus according to the first aspect or the first implementation of the first aspect, the first and second controllable threshold values are controlled in order to minimize a bit error rate.

According to a third implementation of the apparatus according to the second implementation of the first aspect, the first controllable threshold value has an amplitude equal to a sum of M- 1 and a first quantization value and wherein the second controllable threshold value has an amplitude equal to a sum of 1 -M and a second quantization value, the first and second controllable threshold values being controlled by adjusting the first and second quantization values.

According to a fourth implementation of the apparatus according to the third implementation of the first aspect, the first and second quantization values are adjusted so as to have the first and second controllable threshold values varying in a reverse direction or in a same direction.

According to a fifth implementation of the apparatus according to the first aspect or any one of the preceding implementations of the first aspect, the selected amplitude difference is the smallest amplitude absolute difference amongst the first amplitude absolute difference and the second amplitude absolute difference.

According to a sixth implementation of the apparatus according to the fifth implementation of the first aspect, the amplitude difference selection is performed by the most significant bit.

According to a seventh implementation of the apparatus according to the sixth

implementation of the first aspect, an output signal of the three-valued logic unit is given by the following truth table provided that the absolute values of Xi and X2 are strictly greater than M-2, i.e., abs(Xi )>M-2 and abs(X ₂ )>M-2:

where Xi and X ₂ are two consecutive analog data of the M-level signal sampled at a distance of one symbol period with respect to each other, sign(X-i ) and sign(X ₂ ) correspond to the polarity of their respective most significant bit, Xi _q refers to Xi and is a threshold value amongst the first and second controllable threshold values, X _2q refers to X ₂ and is a threshold value amongst the first and second controllable threshold values, sign(Xi-Xi _q ) refers to Xi and corresponds to the polarity of the selected amplitude difference amongst the first and second amplitude differences, and sign(X ₂ -X _2q ) refers to X ₂ and corresponds to the polarity of the selected amplitude difference amongst the first and second amplitude differences. According to an eighth implementation of the apparatus according to the first aspect or any one of the preceding implementations of the first aspect, the M-level signal is an M-pulse amplitude modulation signal.

According to a ninth implementation of the apparatus according to the eighth implementation of the first aspect, the outer level bit is a least significant bit when M equals four.

According to a tenth implementation of the apparatus according to the first aspect or any one of the preceding implementations of the first aspect, the apparatus further comprises a filter adapted to filter the truth value output from the three-valued logic unit, and an oscillator adapted to receive the filtered truth value and generate a clock signal to be provided to the M-level log ₂ (M)-bit ADC.

The above object is also solved in accordance with a second aspect.

According to the second aspect, the invention relates to a method for recovering clock and data from an M-level signal of a receiver in a transmission system, where M is a positive integer and a power of two, and wherein two consecutive analog data of the M-level signal are sampled at a distance of one symbol period with respect to each other. The method comprises the steps of outputting an outer level bit corresponding to a polarity of an amplitude difference between an analog data of the M-level signal and a closest voltage threshold amongst 2-M and M-2, outputting the most significant bit corresponding to a polarity of an amplitude difference between the analog data of the M-level signal and a voltage threshold equal to zero, comparing a first amplitude difference between the analog data and a first controllable threshold value, comparing a second amplitude difference between the analog data and a second controllable threshold value, and outputting, through a truth table, a truth value amongst -1 , 0 and +1 , based on a polarity of the most significant bit, a polarity of the outer level bit and a polarity of an amplitude difference to be selected amongst the first and second amplitude differences.

According a first implementation of the method according to the second aspect, the method comprises the steps of filtering the truth value, receiving the filtered truth value, and generating a clock signal based on the received filtered truth value.

The above object is also solved in accordance with a third aspect. According to the third aspect, the invention relates to a computer program comprising a program code for performing the method according to the second aspect or any one of the implementations of the second aspect when executed on a computer. Thereby, the method can be performed in an automatic and repeatable manner.

The computer program can be performed by the above apparatus. The apparatus can be programmably arranged to perform the computer program.

More specifically, it should be noted that the above apparatus may be implemented based on a discrete hardware circuitry with discrete hardware components, integrated chips or arrangements of chip modules, or based on a signal processing device or chip controlled by a software routine or program stored in a memory, written on a computer-readable medium, or downloaded from a network, such as the internet. The above apparatus may be implemented without signal transmission or receiving capability for simply controlling the transmission or reception function of a corresponding transmitter device or receiver device.

It shall further be understood that a preferred embodiment of the invention can also be any combination of the dependent claims or above embodiments with the respective independent claim.

These and other aspects of the invention will be apparent and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following detailed portion of the present disclosure, the invention will be explained in more detail with reference to the exemplary embodiments shown in the drawings, in which: Fig. 1 shows a schematic block diagram of a simple conventional IM/DD-based PAM-4 transmission system 100, in which the present invention can be implemented;

Fig. 2 shows a time diagram with a schematic eye diagram of a received signal with different sampling phases in the case of an early sampling;

Fig. 3 shows a truth table of a conventional Alexander phase detector; Fig. 4 shows a signal amplitude versus a normalized time (t/U I ) depicting an eye

diagram after equalization of a received PAM-4 signal according to an embodiment of the present invention;

Fig. 5 shows a truth table of a phase detector according to an embodiment of the

present invention; Fig. 6 shows TEDC versus a normalized time (t/UI) at two Rx input powers (OdBm and - l OdBm) according to an embodiment of the present invention;

Fig. 7 shows the corresponding eye diagram of Fig. 6 at a Rx input power of OdBm

according to an embodiment of the present invention; Fig. 8 shows the corresponding eye diagram of Fig. 6 at a Rx input power of -1 OdBm according to an embodiment of the present invention;

Fig. 9 shows a signal amplitude versus a normalized time (t/UI) depicting an eye

diagram after equalization of a received PAM-4 signal at a BER of 0.004 for (a): a 28GBd system receiving an input power of -1 OdBm and (b): a 56GBd system receiving an input power of -4dBm, according to an embodiment of the present invention;

Fig. 10 shows TEDC versus a normalized time (t/UI) for the respective 28GBd and

56GBd systems of Fig. 9 according to an embodiment of the present invention;

Fig. 1 1 shows TEDC versus a normalized time (t/UI) for different pairs of thresholds according to an embodiment of the present invention;

Fig. 12 shows a comparison of the PD performance between a conventional linear phase detector (LPD) and a proposed phase detector (NPD) using (a): an estimated root mean square Jitter (Jrms) versus the input power (Pin) and (b): BER versus Pin, according to an embodiment of the present invention; Fig. 13 shows an assessment of the NPD performance using (a): an eye diagram at a

Pin of 2dBm and (b): TEDC versus a normalized time (t/UI) for two pairs of PD thresholds, according to an embodiment of the present invention;

Fig. 14 shows a comparative BER performance between the default and optimized NPD thresholds with respect to the LPD thresholds, according to an embodiment of the present invention; and

Fig. 15 shows a schematic block diagram of a proposed clock and data recovery device

200 according to an embodiment of the present invention.

Identical reference signs are used for identical or at least functionally equivalent features. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

According to the following embodiments, a new phase detection approach for use in connection with clock and data recovery in multi-level signal transmission systems (e.g., PAM-4, PAM-8 or other PAM-M where M is a number of levels that is a positive integer and a power of two) is provided. The new phase detection approach uses only one sample per symbol, which enables the clock extraction at very high baud (Bd) rates, and can be implemented based on a pure digital architecture with lowest sampling speed to recover the transmitted multi-level signal. Circuit schemes are thus easy to implement as they require only digital circuits and do not have to cope with analog values. The proposed phase detection approach can control sampling phase by adjusting the thresholds of the phase detector (PD) and further enable timing in high-speed systems where the multi-level signal is already available before clock and data recovery. It can be achieved by using high bandwidth components and systems that do not require an enhanced DSP after the ADC block, so that it is suitable for small-size and low-power consumption transceivers. Various embodiments of the present invention will now be described based on a PAM-4 transmission system with an optical fiber. The new algorithm of the proposed new phase detection approach works with a single sample per symbol. The PAM-4 signal levels are equal to -3, -1 , +1 , and +3.

Fig. 4 shows a signal amplitude versus a normalized time (t/U I ) depicting an eye diagram after equalization of a received PAM-4 signal according to a first embodiment of the present invention. The PAM-4 signal is equalized through a CTLE whose parameters are optimized based on a multi-modulus algorithm with a single sample per symbol. The best sampling position is indicated by the dashed arrow "BSP". At that position, the eye diagrams have their maximum opening, so that the best signal-to-noise ratio can be obtained. A rule of the proposed phase detection (PD) scheme is to discard all samples that are in the range of amplitude level from "-2" to "+2" in Fig. 4. This is a so-called bad region. Only two consecutive samples Xi and X2 that are at a distance of 1 Ul and out of said range of amplitude level will be considered for clock and data recovery.

A single sample X is compared to the closest PD outer level X _q , where X _q = Xdown if X _q <0 and Xq=X _U p if X _q >0, and the sign of this operation, namely sign(X _q -X), is used for phase detection output derivation. It should be noted that the PD outer levels need not to be equal to the ADC output levels -3 and +3 in order to allow the sampling phase to be adjusted.

Fig. 5 shows a truth table of a phase detector according to a second embodiment of the present invention. The signal output from the output "OUT" of the phase detector, which corresponds to a truth value amongst -1 , 0 and +1 , may then be filtered through a filter such as a low pass filter (LPF) and used to drive a clock oscillator such as a voltage-controlled oscillator (VCO). The operations defined in the truth table are performed by digital blocks. Provided that the absolute values of two consecutive analog data of the M-level signal sampled at a distance of one symbol period with respect to each other are strictly larger than 2, i.e., abs(Xi)>2 and abs(X2)>2, it can be gathered from the truth table that sign(X-i) and sign(X2) correspond to the respective polarity or sign of X1 and X2, Xi _q denotes X _q referring to Xi, X2q denotes X _q referring to X2, sign(Xi-Xi _q ) refers to Xi and corresponds to the polarity or sign of the difference Xi-Xi _q , and sign(X2-X2 ) refers to X2 and corresponds to the polarity or sign of the difference X2-X2 .

The PD outer levels controlling the sampling phase are optimized in a dithering mode and the best sampling phase (BSP) corresponding to the minimum number of corrected bits output from a FEC block is found. The PD outer levels can also be controlled in order to optimize the PD performance in terms of gain and jitter. A 28GBd PAM-4 system (as shown in Fig. 1 ) with an externally modulated laser (EML) has been simulated. TEDC has been tested in links without chromatic dispersion, with enough bandwidth, and with equalization. Only the receiver (Rx) input power has been varied. As can be seen in the diagram of Fig. 6 showing TEDC versus a normalized time (t/U I ) at two Rx input powers, i.e., at Pin=0dBm and Pin=-10dBm, it could be verified that the TEDC was not significantly affected by a power reduction of l OdBm. The curve is symmetric and without the hang-up region (only at 180° phase). Figs. 7 and 8 show the corresponding eye diagrams at the respective Rx input powers of OdBm and -l OdBm.

The system with EML shown in Fig. 1 is experimentally verified at 28GBd and 56GBd at the received powers corresponding to a BER of 0.004. The received PAM-4 signal is equalized by a FIR filter before the CDR block in order to get a PAM-4 signal with less inter-symbol interference (ISI). Eye diagrams after equalization are shown in Fig. 9 for a Pin of -10 and - 4dBm in 28GBd and 56GBd systems, respectively. The TEDC of those two systems are presented in Fig. 10. As can be seen therefrom, the 56GBd system has a better TEDC (i.e., a higher PD gain) and also less jitter, although not presented herein, because of the existence of stronger signals above the level +3 and below the level -3.

The previous 56GBd data is used to demonstrate the sampling phase adjustment (SPA) by controlling the PD thresholds. To that extent, Fig. 1 1 shows TEDC versus a normalized time (t/UI) for different pairs of thresholds, i.e., for (+3; -3), (+3.3; -2.7) and (+2.7; -3.3). The optimum sampling phase is equal to 0 and TEDC with the thresholds +3 and -3 provides a sampling phase that is slightly shifted towards the right with respect to said optimum sampling phase. The thresholds +3.3 and -2.7 also shift the TEDC towards the right with respect to said optimum sampling phase. Indeed, a better sampling phase is achieved by the thresholds +2.7 and -3.3. However, moving the sampling phase may increase the jitter, so that a trade-off between these two effects must be considered. For example, the thresholds +2.9 and -2.9 do not change the sampling phase but improve the clock performance by providing a higher PD gain and less self-jitter.

In a 56GBd experiment with a 4MHz phase-locked loop (PLL) bandwidth and as shown in Fig. 12, the performance of the proposed phase detector (hereafter denoted by NPD) according to an embodiment of the present invention has been compared to a conventional linear phase detector (hereafter denoted by LPD) using an estimated root mean square jitter (Jrms) and a BER. As can be seen in Fig. 12(a) showing the characteristics of Jrms versus the input power (Pin), the NPD introduces more jitter than the LPD. As can be seen in Fig. 12(b) showing the characteristics of BER versus the input power (Pin), the NPD is more susceptible to BER degradation than the LPD. However, the jitter degradation is not so serious and cannot cause such a BER degradation, so that it likely comes from the sampling phase.

In the above 56GBd experiment and as shown in Fig. 13, the performance of the NPD according to an embodiment of the present invention has been assessed using (a): an eye diagram at a Pin of 2dBm and (b): TEDC versus a normalized time (t/UI) for two pairs of PD thresholds. As can be seen in Fig. 13(a), the eye diagram is skewed since the upper eye is slightly shifted towards the left whereas the lower eye is moved towards the right. Moreover, the TEDC diagram shown in Fig. 13(b) for the default PD thresholds +3 and -3 indicates that the sampling phase will be shifted by about 0.02UI, thereby causing a BER degradation. Nevertheless, Fig. 13(b) also shows that the TEDC is getting shifted towards the left at the exact position corresponding to the best BER by setting the two PD thresholds to optimized thresholds +2.8 and -3.2.

Fig. 14 shows a comparative BER performance between the default and optimized NPD thresholds with respect to the LPD thresholds. The BER performance of the NPD with optimized thresholds (i.e., +2.8 and -3.2) and LPD is almost the same. No performance degradation with the NPD, which works only with a single sample per symbol and uses

MSBs and the signs of quantization errors with the optimum PD thresholds, can be observed.

Fig. 15 shows a schematic block diagram of the proposed clock and data recovery (CDR) device 200 according to an embodiment of the present invention. The proposed CDR device 200 according to the embodiment comprises a PAM-4 2-bit ADC 210 and a phase detector (PD) 220.

The input of the CDR device 200 receives a PAM-4 signal (Rx PAM-4), which is identically provided to three voltage comparators 21 1 -213 of the PAM-4 2-bit ADC 210 and two voltage comparators 221 -222 of the PD 220.

The first voltage comparator 21 1 compares a first amplitude difference corresponding to an amplitude difference between an analog data (X) of the PAM-4 signal and a voltage threshold equal to +2 as to output the least significant bit (LSB+, ±1 ) corresponding to the polarity (±) or sign (±) of the first amplitude difference. The second voltage comparator 212 compares a second amplitude difference corresponding to an amplitude difference between the analog data (X) of the PAM-4 signal and a voltage threshold equal to -2 as to output the least significant bit (LSB-, ±1 ) corresponding to the polarity (±) or sign (±) of second amplitude difference.

The third voltage comparator 213 compares a third amplitude difference corresponding to an amplitude difference between the analog data (X) of the PAM-4 signal and a voltage threshold equal to 0 as to output the most significant bit (MSB, ±1 ) corresponding to the polarity (±) or sign (±) of the third amplitude difference.

The output (LSB+, LSB-, MSB) of each of these voltage comparators 21 1 -213 is temporarily stored in respective D-type flip-flops 214-216, to which they are connected. Afterwards, the output (MSB) of the third voltage comparator 213 selects, through a first selector 217, the correct outer level bit (OLB, ±1 ), which specifically corresponds to a least significant bit (LSB, ±1 ) in the case of a 2-bit ADC, amongst LSB+ and LSB-, namely the outer level bit (OLB, ±1 ) corresponding to the polarity (±) or sign (±) of the amplitude difference between the analog data (X) of the PAM-4 signal and the closest voltage threshold amongst -2 and +2. Thereby, the PAM-4 2-bit ADC 210 can output a 2-bit data (DATA: MSB, LSB/OLB) according to the truth table depicted above the D-type flip-flop 226. It should be noted that the first voltage comparator 21 1 is connected in an inverting mode as to invert its output and thus generate a Gray encoded signal.

The fourth voltage comparator 221 compares a fourth amplitude difference corresponding to an amplitude difference between the analog data (X) of the PAM-4 signal and a first controllable threshold value (X _q =X _U p) whose amplitude is equal to a sum of +3 and a first quantization value (Δ1 ). The fifth voltage comparator 222 compares a fifth amplitude difference corresponding to an amplitude difference between the analog data (X) of the PAM-4 signal and a second controllable threshold value (X _q =Xdown) whose amplitude is equal to a sum of -3 and a second quantization value (Δ2). The first and second controllable threshold values (X _u , Xdown) are controlled by using, for example, an outer decoder such as a FEC 240 or some known training sequence during the calibration phase, in order to minimize the BER, and adjusted accordingly as to obtain optimized threshold values. The optimization process of the thresholds can be performed through a PD optimization and/or a sampling phase optimization. In the PD optimization, the first and second controllable threshold values (X _u , Xdown) are firstly varied in opposite directions until reaching the optimum PD performance (i.e., minimum BER after FEC 240). In this way, the sampling phase does not vary while the PD gain and jitter are controlled. The optimized threshold values can then be -2.9, which is obtained by increasing -3, and +2.9, which is obtained by decreasing +3. In the sampling phase optimization, the first and second controllable threshold values (X _u , Xdown) are firstly varied in same directions until reaching the optimum PD performance (i.e., minimum BER after FEC 240). In this way, the sampling phase varies together with the PD gain and jitter. The optimized threshold values can then be -2.7, which is obtained by increasing -3, and +3.3, which is obtained by increasing +3.

The output of each of these fourth and fifth voltage comparators 221 , 222 is temporarily stored in respective D-type flip-flops 223, 224, to which they are connected. Afterwards, the output (MSB) of the third voltage comparator 213 selects, through a second selector 225, a polarity (±) or sign (±) of the smallest amplitude absolute difference amongst the fourth amplitude difference and the fifth amplitude difference.

Furthermore, some D-type flip-flops 226-228 and logical blocks 229-233 are added to generate the PD output (OUT) through a three-value logic unit 234, which outputs a truth value amongst -1 , 0 and +1 according to the truth table of Fig. 5.

More specifically, the three-value logic unit 234 provides the digital output "±1 " of the XOR gate 229 if the output of the AND gate 233 is in an active state corresponding to "1 ", and provides the digital output "0" of the XOR gate 229 if the output of the AND gate 233 is in an inactive state corresponding to "0". Thus, the logical output "0" of the AND gate 233 reflects the last row denoted "otherwise" in the truth table of Fig. 5. The XOR gate 229, with its two input signals corresponding to MSB and the selected amplitude difference amongst the first and second amplitude differences, reflects the remaining upper eight rows of the truth table in Fig. 5. Thus, all blocks after the five voltage comparators 21 1 -213 and 221 -222 are digital.

The PD output (OUT) is then filtered through a filter such as a low-pass filter (LPF) 241 and used for driving a voltage-controlled oscillator (VCO) 242.

Although the present invention has been specifically described in connection with a PAM-4 transmission system, it should be noted that the present invention can be used in any multilevel transmission systems with M levels, where M is a positive integer and a power of two. By generalizing to M levels, the clock and data recovery (CDR) apparatus would comprise an M-level log2(M)-bit ADC consisting of (2 ^{i052 ( )} - 1) voltage comparators. For example, it could be implemented in a PAM-8 transmission system with M=8 levels denoted -7,-5,-3, -1 , +1 , +3, +5, and +7, wherein all samples that would be in the range of amplitude level from "- 6" to "+6" would be discarded. The block diagram of Fig. 15, which is valid for M=4, would then have to be modified for M=8. In particular, the PAM-4 2-bit ADC 210 would be replaced by a PAM-8 3-bit ADC consisting of seven comparators, and the outer levels +2 and -2 of the corresponding comparators 21 1 and 212 would be respectively replaced by the outer levels +6 and -6. In addition, the PAM-8 3-bit ADC would output a 3-bit data (DATA) according to the following truth table:

As already mentioned, one comparator output in Fig. 15 can be inverted due to Gray mapping of the PAM-4 signal, and this is efficiently used for the Gray decoding and the logic enabling the detection of signals below the level -2 and above the level +2. In the case of a PAM-8 transmission system, more comparator outputs should be inverted when the Gray decoding is performed. The corresponding Gray codes would be then: "000", "001 ", "01 1 ", "010", "1 10", 1 1 1 ", "101 " and "100".

Regarding the phase detector, the first controllable threshold value X _u would have an amplitude equal to a sum of +7 and a first quantization value (Δ1 ), and the second controllable threshold value Xdown would have an amplitude equal to a sum of -7 and a second quantization value (Δ2).

The same logical circuitry would be used, so that all D-type flip-flops, all logical blocks and the three-valued logic unit would remain unchanged. In summary, the present invention relates to an apparatus and method for recovering clock and data from an M-level signal of a receiver in a transmission system, M being a positive integer and a power of two, wherein an outer level bit (OLB) corresponding to a polarity (±) or sign (±) of an amplitude difference between an analog data (X) of the M-level signal and a closest voltage threshold amongst 2-M and M-2 is output, the most significant bit (MSB) corresponding to a polarity (±) or sign (±) of an amplitude difference between the analog data (X) of the M-level signal and a voltage threshold equal to zero is output, a first amplitude difference between the analog data (X) and a first controllable threshold value (X _u ) is compared, a second amplitude difference between the analog data (X) and a second controllable threshold value (Xdown) is compared, a truth value amongst -1 , 0 and +1 , based on a polarity (±) or sign (±) of the most significant bit (MSB), a polarity of the outer level bit (OLB) and a polarity of an amplitude difference to be selected amongst the first and second amplitude differences is output through a truth table, and two consecutive analog data (Xi, X2) of the M-level signal are sampled at a distance of one symbol period with respect to each other. While the invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The invention is not limited to the disclosed embodiments. From reading the present disclosure, other modifications will be apparent to a person skilled in the art. Such modifications may involve other features, which are already known in the art and may be used instead of or in addition to features already described herein. In particular, the present invention can be applied to any multilevel transmission system. More specifically, the transmission system is not restricted to an optical transmission system. Rather, the present invention can be applied to any wired or wireless coherent or non-coherent transmission system. The transmitter and receiver device of the proposed system can be implemented in discrete hardware or based on software routines for controlling signal processors at the transmission and reception side.

The invention has been described in conjunction with various embodiments herein. However, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless

telecommunication systems.

Although the present invention has been described with reference to specific features and embodiments thereof, it is evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded simply as an illustration of the invention as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations or equivalents that fall within the scope of the present invention.