EARLY TO LATE VOTE RATIOS

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Application No. 17/220,786, filed April 1, 2021, entitled “CLOCK AND DATA RECOVERY LOCK DETECTION CIRCUIT FOR VERIFYING LOCK CONDITION IN PRESENCE OF IMBALANCED EARLY TO LATE VOTE RATIOS”, all of which are hereby incorporated herein by reference in their entirety for all purposes.

REFERENCES

[0002] The following prior applications are herein incorporated by reference in their entirety for all purposes:

U.S. Patent Application No. 16/274118, filed June 12, 2019, now U.S. Patent 10,488,227 granted November 26, 2019, naming Kiarash Gharibdoust, entitled “Low Latency Combined Clock Data Recovery Logic Network and Charge Pump Circuit”, hereinafter identified as [Gharibdoust]

BACKGROUND

[0003] It is common for communications receivers to extract a receive clock signal from the received data stream. Some communications protocols facilitate such Clock Data Recovery (CDR) operation by constraining the communications signaling so as to distinguish between clock-related and data-related signal components. Similarly, some communications receivers process the received signals beyond the minimum necessary to detect data, so as to provide the additional information to facilitate clock recovery. As one example, a so-called double-baud-rate receive sampler may measure received signal levels at twice the expected data reception rate (i.e. utilizing two distinct time samples per receive unit interval,) to allow independent detection of the received signal level corresponding to the data component, and the chronologically offset received signal transition related to the signal clock component. [0004] However, the introduction of extraneous communications protocol transitions limits achievable data communication rate. Similarly, receive sampling at higher than transmitted data rate substantially increases receiver power utilization. Thus, a receive CDR system operating at baud rate (e.g. the receiver utilizing only a single time sample per receive unit interval) is desirable.

[0005] Data-dependent receive equalization is also well known in the art. Generally, these time- domain-oriented equalization methods focus on compensating for the effects of inter-symbol- interference or ISI on the received signal. Such ISI is caused by the residual electrical effects of a previously transmitted signal persisting in the communications transmission medium, so as to affect the amplitude or timing of the current symbol interval. As one example, a transmission line medium having one or more impedance anomalies may introduce signal reflections. Thus, a transmitted signal will propagate over the medium and be partially reflected by one or more such anomalies, with such reflections appearing at the receiver at a later time in superposition with signals propagating directly.

[0006] One method of data-dependent receive equalization is Decision Feedback Equalization or DFE. In DFE, the time-domain oriented equalization is performed by maintaining a history of previously-received data values at the receiver, which are processed by a transmission line model to predict the expected influence that each of the historical data values would have on the present receive signal. Such a transmission line model may be pre-calculated, derived by measurement, or generated heuristically, and may encompass the effects of one or more than one previous data interval. The predicted correction of the accumulated influence of these one or more previous data intervals is collectively called the DFE compensation. At low to moderate data rates, the DFE compensation may be calculated in time to be applied before the next data sample is detected, as example by being explicitly subtracted from the received data signal prior to receive sampling, or implicitly subtracted by modifying the reference level to which the received data signal is compared in the receive data sampler or comparator. However, at higher data rates the detection of previous data bits and computation of the DFE compensation may not be complete in time for the next data sample, requiring use of so-called “unrolled” DFE computations performed on speculative or potential data values rather than known previous data values. As one example, an unrolled DFE stage may predict two different compensation values depending on whether the determining data bit will resolve to a one or a zero, with the receive detector performing sampling or slicing operations based on each of those predictions, the multiple results being maintained until the DFE decision of the prior unit interval is resolved. [0007] [Gharibdoust] describes a data communication receiver incorporating at least one stage of unrolled DFE, thus for each receive unit interval a single clock signal initiates two concurrent samples, one representing the received data result if the previous unit interval was a one, and the other representing the received data result if the previous unit interval was a zero. Because of the speculated influence of the previous unit interval data, the sampling thresholds at which the two concurrent measurements are made are offset in amplitude. For certain sequences of received data, it is possible for a received signal transition to pass through a first sampler’ s threshold voltage at the sampling time, while a second sampler obtains a stable “center of eye” data result. Said first sampler response may be processed to obtain an indication whether the actual received signal transition was earlier or later than would be predicted relative to the receive clock, providing a correction signal that may be used to adjust the receive clock phase.

BRIEF DESCRIPTION

[0008] Methods and systems are described which identify whether a receive clock signal is properly locked in frequency and phase to a receive signal stream, permitting error-free data detection to occur. Following conventional practices, the frequency and phase of a receive clock is adjusted based on “early” or “late” error indications obtained by observing transitions in a received signal stream, said adjustments accumulating until the transition timing of the receive clock is sufficiently accurate to maintain data detection. Due to inherent processing biases within the receive clock system and/or intentional clock rate variations generated by the transmitting device, there may be a variation between the number of “early” error indications and the number of “late” error indications observed, even when the receive clock phase is accurately adjusted. Integration or accumulation of error indications over two or more time intervals may be used to determine whether the receive clock is locked, in one embodiment by observing that the accumulated error indications are within a predetermined range, in a second embodiment by observing that the ratios of error indicators are within a predetermined range, and in another embodiment by observing that consecutive accumulated error indications are similar.

[0009] Methods and systems are described herein for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote ratios, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote ratios are within a predetermined threshold.

BRIEF DESCRIPTION OF FIGURES

[0010] FIG. l is a block diagram of a high speed data communications receiver.

[0011] FIG. 2 is a block diagram of a Clock Data Recovery subsystem, as incorporated in the receiver of FIG. 1.

[0012] FIGs. 3 A shows typical received signals in a receiver utilizing one stage of unrolled DFE. FIG. 3B illustrates use of the unrolled DFE samplers to obtain transition information.

[0013] FIG. 4 is a flowchart of a method 400, in accordance with some embodiments.

[0014] FIG. 5 is a block diagram of an apparatus, in accordance with some embodiments.

[0015] FIG. 6 depicts block diagrams of an early-late vote difference counter and an early-late vote summation counter, in accordance with some embodiments.

DETAILED DESCRIPTION

[0016] In recent years, the signaling rate of high speed communications systems have reached speeds of tens of gigabits per second, with individual data unit intervals measured in picoseconds. Conventional practice for a high-speed integrated circuit receiver has each data line terminate (after any relevant front end processing such as amplification and frequency equalization) in a sampling device. This sampling device performs a measurement constrained in both time and amplitude dimensions; in one example embodiment, it may be composed of a sample-and-hold circuit that constrains the time interval being measured, followed by a threshold detector or digital comparator that determines whether the signal within that interval falls above or below (or in some embodiments, within bounds set by) a reference value. Alternatively, a digital comparator may determine the signal amplitude followed by a clocked digital flip-flop capturing the result at a selected time. In other embodiments, a combined time- and amplitude- sampling circuit is used, sampling the amplitude state of its input in response to a clock transition.

[0017] FIG. 1 illustrates a high-speed data receiver in accordance with some embodiments herein, in which input signals ‘Rx in’ undergo front end processing 110 and 120 before sampled using speculative samplers 131/133 and 141/143 in parallel processing phases 130 and 140 respectively, the parallel processing phases 130 and 140 operating on alternating receive unit intervals as depicted by sampling clocks phOOO and phi 80, which may be derived from VCO clocks ClkOOO and Clkl80, respectively. It should be noted that the use of additional or fewer parallel processing phases may be adapted to the receiver of FIG. 1, e.g., FIG. 1 may be similarly composed of a single processing phase or additionally four (or more) parallel processing phases being interleaved by additional multiplexers similar to multiplexers 150 and 160.

[0018] As shown in the receiver of FIG. 1, samplers 131 and 133 of parallel processing phase 130 generate two samples: one generated according to the +vhl threshold and one according to the - vhl threshold. Once the data bit in the preceding interval is fully resolved, one of samples 132 and 134 is selected as a data decision 138 and is provided to multiplexer 150 while the other is selected as a potential edge sample candidate 139 (pending pattern verification) and provided to multiplexer 160. In some embodiments utilizing two parallel processing phases as shown in FIG. 1, the data decisions 138 and 148 may also be cross-communicated as selection inputs to multiplexers 145 and 135, respectively (not shown). In alternative embodiments, the selection inputs to multiplexers may be provided by another means, e.g., from history buffer 190. Samplers 141/143 generating outputs 142 and 144 and multiplexer 145 of parallel processing phase 140 operate similar to those of parallel processing phase 130.

[0019] Multiplexer 150 alternates between providing data decisions Dn 155 corresponding to data decisions 138 and 148 generated by parallel processing phases 130 and 140, respectively, according to MuxClk. The data decisions Dn 155 are stored in data history buffer 190 and may also have additional historical DFE correction applied by DFE correction circuit 170 which operates on historical data decisions provided by history buffer 190. Multiplexer 160 alternates between providing possible edge samples 139 and 149 from processing phases 130 and 140 as potential edge sample candidates Edge _n 165 to CDR circuit 180, which is described in further detail with respect to FIGs. 2 and 5. The ‘n’ subscripts herein refer to the signaling interval for which the sample was taken. In some embodiments, pattern detection circuit 195 generates an early-late vote E/L based on Edge _n and one or more data samples stored in history buffer 190 as well as a data pattern detection signal indicating that the early-late vote E/L is valid. The early- late vote E/L and the data pattern detection signal may be provided to the CDR 180 for updating the VCO.

[0020] Subsequently, this document will use the term sampling device, or more simply “sampler” to describe this receiver component that generates the input measurement, as it implies both the time and amplitude measurement constraints, rather than the equivalent but less descriptive term “sheer” also used in the art. The well-known receiver “eye plot”, an example of which is shown as FIG. 3A, graphically illustrates input signal values that will or will not provide accurate and reliable detected results from such measurement, and thus the allowable boundaries of the time- and amplitude-measurement windows imposed on the sampler.

Clock Data Recovery

[0021] So-called Clock Data Recovery or CDR circuits support such sampling measurements by extracting timing information, as one example from signal transitions on the data lines themselves and utilizing that extracted information to generate clock signals to control the time interval used by the data line sampling device(s). The actual clock generation may be performed using well known circuits such as a Phase Locked Loop (PLL) or Delay Locked Loop (DLL), which in their operation may also generate higher frequency internal clocks, multiple clock phases, etc. in support of receiver operation. The example embodiment of FIG. 2 uses a PLL composed of phase comparator 220, Low-pass filter 230, and voltage-controlled ring oscillator (VCO) 240.

[0022] In some embodiments, CDR involves two interrelated operations; generation of a local clock signal having a known phase relationship with the received signal, and derivation of a properly timed sampling clock from that local clock. Such indirect synchronization may occur if the receiver operates at a different rate than the received data, as one example utilizing two alternating receive processing phases, each operating at one half the receive data rate. Furthermore, the naturally locked phase relationship between the signal used as an external phase reference and the local clock may be quite different from the desired sample clock timing, relative to that same local clock, thus requiring the sampling clock to be generated with a predetermined amount of phase offset. In the CDR of FIG. 2, this phase offset is controlled by phase interpolator 260.

[0023] As the optimum “center of open eye” data sampling point is difficult to measure directly, most systems instead initiate the data sampling operation at a predetermined delay or offset from the eye edge, i.e. when the input signal transitions between states. Typically, the steps associated with CDR include identification of suitable receive signal transitions, comparison of timing of said transitions with the local clock signal so as to produce a phase error signal, correction of the local clock signal using the phase error signal, and derivation of a properly timed sampling clock from the corrected local clock signal. [0024] A CDR system may include a phase detector comparing the external timing reference with the local clock (e.g. the PLL’s VCO output or a clock derived from its VCO output) to produce a phase error signal, a low-pass filter that smooths the phase error to produce a VCO control signal, and a voltage-controlled oscillator (VCO) producing a continuous clock oscillation at the controlled rate. Historically, such PLLs were implemented as closed loop analog systems, thus the frequency control of the VCO was an analog voltage derived from a low-pass filter operating on the (typically pulse-width-modulated) error results from the phase detector. This analog-oriented nomenclature persists without implying limitation, even though in some embodiments all or some of these circuit elements are fully digital designs and all or some of the control signals are digital values or signals.

Decision Feedback Equalization

[0025] It has become common practice for data communications receivers to incorporate Decision Feedback Equalization (DFE) to compensate for signal propagation anomalies in the communications medium. The DFE system performs time-domain oriented equalization on the received signal by maintaining a history of previously-received data values at the receiver, and processing those historic data values with a transmission line model to predict the expected influence each of the historical data values would have on the present receive signal. Such a transmission line model may be pre-calculated, derived by measurement, or generated heuristically, and may encompass the effects of one or more than one previous data interval. The predicted influence of these one or more previous data intervals is collectively called the DFE compensation, which is subsequently applied to the received signal to facilitate the current unit interval’s detection. For purposes of explanation, this computation may be simply described as comprising multiplication of each previous unit interval’s data value by a predetermined scaling factor or weight, with the summation of these scaled results producing a composite DFE compensation value representing the cumulative predicted effect of all such previous unit intervals.

[0026] In some receiver designs, this DFE compensation value will be subtracted from the current receive signal input, to produce a corrected signal more accurately representing the received data value. Such subtraction may be performed, as one example, by applying the received signal and the DFE compensation value to the inputs of a differential amplification circuit. In one common embodiment, this differential circuit represents the input of a digital comparator or a combined time- and amplitude- sampler, the output of which represents the detected data value relative to a particular speculative threshold level. [0027] Those familiar with the art will recognize that the DFE compensation value produced as described above cannot be calculated until the previous unit interval’s data value has been detected. Thus, as data rates increase, a point will be reached at which the information to produce the DFE compensation value is not available in time to be applied to the next unit interval sampling. Indeed, at the highest data rates currently used in practice, this situation may exist for multiple previous unit intervals, as the detection time for a single data value may represent multiple unit interval durations, requiring the receiver to pipeline or parallelize the detection operation. Thus, it is common for embodiments to forgo such “closed loop” DFE methods for one or more of the most recent unit intervals. Instead, such embodiments speculatively generate one or more elements of the DFE compensation value as “open loop” or “unrolled loop” operations. As one example, an embodiment described in [Gharibdoust] and incorporated here as FIG. 1 utilizes multiple simultaneously-clocked data detection samplers, each sampler provided with a distinct speculative value of DFE compensation associated with the possible detected data value for one or more previous unit intervals. In such an embodiment, selection of one of the speculative DFE compensation values may be postponed until after the current unit interval data detection, by storing the results of the various sampler outputs 132, 134, 142, 144 (which are dependent on different speculative DFE compensation values) and then later selecting via e.g., multiplexers 135 and 145 which stored output is to be used for data detection 138/148 and which output is a potential edge sample candidate 139/149.

Baud-rate CDR in a speculative DFE system

[0028] Under some operating conditions, the “extra” unrolled DFE stored results not selected for data detection may provide timing information as to the relationship of the sampling clock and receive signal transitions. As described in [Gharibdoust] and shown here as FIG. 3B, the signal trajectory for some receive data patterns may pass through an unrolled DFE sampler threshold at its sampling time, while another DFE sampler measuring at a different threshold at the same sampling time detects a stable “center of open eye” data result. In FIG. 3B, this may be seen for samples 310, in which the upper sample (subsequently described as the data sampler) is taken in the center of the data eye, while the lower sampler (subsequently described as the edge sampler) intersects with the signal trajectory, in this example for a signal corresponding to a “1” previous data value, a “0” current value, and a “0” subsequent value, indicated in the illustration by the notation [1, 0, 0] The value obtained by the edge sampler is dependent on the timing relationship between the sample clock and the data edge, as may be seen with samples 305 showing the clock occurring early relative to the data transition, and samples 315 showing the clock occurring late relative to the data transition. [Gharibdoust] describes an exemplary logic implementation that combines the signal trajectory information obtained from a data history buffer and the result obtained from the edge sampler to produce the desired “early” or “late” error indications.

[0029] Although this CDR technique utilizing only a single sampling clock for both clock and data recovery efficiently minimizes the number of samplers required and their inherent power consumption, it provides only intermittent clock phase correction signals, associated with arrival of the particular receive signal patterns to which it is sensitive. Referring to the previously- mentioned analog PLL example, such a phase detector would be enabled only for particular receive signal patterns, resulting in, as one example, a positive or negative pulse output from a phase detector/charge pump which incrementally increases or decreases the integrated signal stored in the low pass filter. Between these phase corrections, the phase detector/charge pump is inhibited, leaving the error voltage produced by the low pass filter unchanged; thus allowing the receive clock PLL to free-run at its last adjusted rate. As previously noted this description is not limiting, with multiple equivalent embodiments in both analog and digital realms known in the art.

PLL lock detection

[0030] During startup or after a prolonged absence of phase corrections, the PLL VCO frequency may be significantly offset from the proper receive clock rate and phase, making it impossible to properly detect receive data.

[0031] As an indication of this fault condition, a lock detection circuit may be used to report when a suitable receive clock is available and thus that the detected data results are reliable. Typically, such circuits observe the error signal controlling the VCO frequency, with a minimization of error signal variations (i.e. an unchanging low-pass filtered error voltage, in an analog PLL) indicating that the present VCO frequency is aligned with the received data stream. However, both intentional and unintentional anomalies may lead such a lock detector to produce false results. Capacitor leakage in the low-pass filter can cause the error signal to drift towards Vss and require periodic “pumping up”, and imbalance between the “pump up” and “pump down” currents in the charge pump output of the phase detector can introduce asymmetric ramp variations in the steady state error voltage that may be mistaken for “lock hunting” behavior in the PLL.

[0032] Some lock detectors combine such error voltage monitoring with clock rate frequency measurement to minimize false lock reports during startup transients and eliminate false locking of the VCO to a fraction or a multiple of the desired frequency. However, even simple frequency measurements can also fail in subtle ways; if the receive clock is asynchronous or pleisochronous to the reference clock used by the counting operation, there can be count ambiguities caused by the arbitrary phase relationship between the beginning and end of the period being measured and the counting clock. Also, many communications systems now intentionally dither the clock frequency used by external signals to minimize peaks in the emitted radiation spectrum. Thus, the measured data rate in a system with such spread-spectrum clocking (SSC) may be significantly offset from the nominal design frequency, with the offset varying periodically over time.

[0033] In one example embodiment, a method includes generating early and late votes for a clock recovery system. As described above, each early and late vote may be associated with a detected transitional data pattern, where a sample generated by one of samplers 131 and 133 as compared to the detected transitional data pattern to determine if the sample is early or late. The method further includes generating a first early-late vote measurement reflective of an imbalance between early and late votes that are generated during a first time interval. The method further includes generating a second early-late vote measurement reflective of an imbalance between early and late votes generated during a second time interval. The method further includes comparing the first and the second early-late vote measurements and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.

[0034] In some embodiments, the first and second time intervals may be determined by a predetermined number of signaling intervals. In such embodiments, generating the first and second early-late vote measurement may include normalizing the early and late votes generated during the first and second time intervals respectively by the predetermined number of signaling intervals that define the first time interval. Normalizing the early and late votes generated during the first and second time interval may include dividing at least one of (i) the early votes (ii) the late votes and (iii) a difference between the early and the late votes by a total number of early and late votes generated during the first and second time interval.

[0035] In at least one alternative embodiment, the first and second time intervals may be determined by a predetermined number of consecutively-generated early and late votes generated from different portions of the data stream. Such embodiments may directly calculate the first and second early-late vote measurements without normalizing as described above. If the total number of early-late votes detected is the same for the first and second time intervals, the CDR-lock detection circuit may be configured to compare at least one of (i) early votes generated in the first and second time intervals, (ii) late votes generated in the first and second time intervals, and (iii) a difference between early and late votes generated in the first and second time intervals.

[0036] In some embodiments, the first and second time intervals are separated by a third time interval. Separating the first and second time intervals with the third time interval allows for the first and second early-late vote measurements to be taken at different points during the data stream, facilitating a more accurate representation of the data stream as a whole.

[0037] As illustrated by the flow chart of FIG. 4, early and late (i.e. clock edge before receive data transmission, clock edge after receive data transmission on qualified data patterns) phase error indications may be counted 410 separately by a early phase counter and a late phase counter, obtaining a first vote count of early and late volts over this first time interval. The first time interval may be determined by counting the number of receive unit intervals, by timing a duration, or by the number of phase error indications obtained. A first early-late vote measurement is determined 430 when the first time interval is over 420, which is reflective of an imbalance between early and late votes counted during this first measurement interval. In embodiments described herein, early- late vote “measurements” may also be referred to as “ratios”, however such measurements and ratios are termed to reflect the imbalance between early and late votes being accumulated in a given time period. In some embodiments, the “measurements” or “ratios” may correspond to a calculated difference in early votes to late votes, while other embodiments may determine such measurements e.g., by analyzing the number of early (or late) votes accumulated relative to a total number of early and late votes accumulated. Further embodiments might store early and late votes separately and perform a ratiometric division between the two to determine the early-late vote measurements.

[0038] The measurement process is repeated for a second time interval, obtaining a second vote count 440 of early and late votes over this second time interval, and a second early-late vote measurement is determined 460 when the second time interval is over 450. In some embodiments, the first and second time intervals are separated by a third time interval, helping to eliminate false counts due to asynchronous period ambiguities and other measurement anomalies as previously described. Furthermore, the first and second early-late vote measurements correspond are associated with different portions of the data stream, and separating them by the third time interval may provide more reliable results as the second early-late vote measurement may not be affected by an anomaly that affected e.g, the first early-late vote measurement. [0039] If the first and the second early-late vote measurements are comparable within a predetermined threshold 470, a CDR lock signal indicating CDR lock may be output. In some embodiments, frequency counter 550 may assist in outputting the CDR lock signal.

[0040] Physical embodiments of this method may be implemented using hardware counters or counters augmented by processing software running on an embedded CPU, management processor, or finite state machine.

[0041] In some alternative embodiments, the early-late vote measurement comparison may be made by direct comparison of the first early-late vote measurement and the second early-late vote measurement, subtraction of the first early-late vote measurement and second early-late vote measurement, and taking a ratio of the first early-late vote measurement and the second early-late vote measurement. Utilizing a threshold comparison rather than absolute equivalence accounts for random measurement errors previously described.

[0042] A further embodiment compares one or more of the early-late vote measurement against predetermined limits to additionally qualify the measurement validity. Another embodiment compares the early-late vote measurement by determining that a ratio or comparison of the first early-late vote measurement to the second early-late vote measurement is within a predetermined threshold. Another embodiment takes early-late vote measurements by separately determining a difference between early and late votes, either using an up/down counter driven by early and late votes, or by subtraction of the measured early and late values. A further embodiment normalizes at least one of the early vote count, late vote count, and/or early-late ratios relative to the total number of votes during the measurement interval.

[0043] In another embodiment, the first measurement interval is separated from the second measurement interval by a third time interval.

[0044] A further embodiment performs a clock frequency measurement of at least one of a clock derived from the VCO clock or a receive sampling clock generated by the PLL, using a known reference such as a system clock or time reference. Such embodiments may additionally qualify output of a CDR lock indication based on the clock frequency measurement being within predetermined values, or differing from an expected value by a predetermined threshold amount.

[0045] FIG. 5 is a block diagram of an apparatus performing CDR-lock verification, in accordance with some embodiments. As shown, FIG. 5 includes early/late logic 505 configured to provide an early-late vote by determining whether or not the edge sample candidate in the current time interval (Edge _n ) is the same or different than the data decision generated in the previous time interval (D _n -i). If Edge _n is equal to Dn-1, then the edge sample is early, while if Edge _n is opposite of D _n -i then the edge sample is late. FIG. 3B illustrates such a relationship by illustrating sampling times before 305 and after 315 the “locked” sampling point 310. It should be noted that additional methods of generating early-late votes may be used, including comparing sampler results to data pattern polarity (e.g., an upward transition versus a downward transition).

[0046] FIG. 5 also depicts an accumulator 525 that includes (i) an early-late vote difference counter 530 for determining effective early-late vote measurements between early and late votes generated in a given time interval and (ii) an early-late vote summation counter 540 or determining a total number of early and late votes generated in the given time interval. As shown, both counters 530 and 540 receive early-late votes E/L from early/late logic 505 and are enabled according to a data pattern detection signal generated by pattern detection logic 195 that includes AND gates 510/515 and OR gate 517. The pattern detection logic 195 utilizes specified inverting and non inverting inputs for AND gates 510/515 receiving three consecutive data decisions D _n -i, D _n , and D _n+i to verify that either one of two possible transitional data patterns occurred, thus validating the early-late vote. In FIG. 5, pattern detection logic 195 is searching for transitional data patterns [1,0,0] or [0,1,1], however it should be noted that additional transitional data patterns may be searched utilizing similar configurations of AND gates 510 and 515. The data pattern detection signal thus enables early-late vote difference counter 530 to increment or decrement based on the result of early/late logic 505. FIG. 6 illustrates one particular embodiment of early-late vote difference counter 530. As shown in FIG. 6, early-late vote difference counter 530 is configured to increment the LSB of multi-bit register 610 when E/L is equal to ‘ V (i.e., Edge _n is late) and to decrement the LSB of multi-bit register 610 when E/L is equal to ‘O’ (i.e., Edge _n is early). The LSB is only adjusted responsive to detection of a valid transitional data pattern as described above via a data pattern detection signal provided to the enable input ‘en’. The multi -bit register 610 is updated for the duration of the given time interval, and upon termination of the time interval (e.g., by interval counter 560), the value of multi -bit register 610 corresponds to a difference between the early and late votes generated during the time interval. The imbalance or difference between the early and late votes may reflect the early-late vote ratio of said time interval, although further processing may be included as described in more detail below.

[0047] FIG. 6 also includes an exemplary embodiment of early-late vote summation counter 540 that includes multi-bit register 620. Early-late vote summation counter 540 may operate in a similar manner as the early-late vote difference counter 530, however, multi-bit register 620 is always incremented regardless of the value of the early-late vote E/L, where each incremental operation occurs responsive to detection of a valid transitional data pattern as described above. Thus, upon termination of the time interval, the value of multi-bit register 620 corresponds to a total number of early and late votes generated during the time interval, and the value may be transferred to another multi-bit register in CDR-lock detection circuit 570. In some embodiments, the time interval may correspond to a predetermined number of signaling intervals using e.g., interval counter 560. Alternatively, the time interval may be determined by a predetermined number of early and late votes generated in a set of consecutive transitional signaling intervals (i.e., signaling intervals associated with one of the aforementioned transitional data patterns, such signaling intervals only being separated by signaling intervals for which there is not a transition). In such embodiments interval counter 560 may be omitted, and once early-late vote summation counter 540 reaches the predetermined number of early and late votes generated in the set of consecutive transitional signaling intervals, the value of early-late vote difference counter 530 may be stored in CDR-lock detection for determination of the CDR-lock signal.

[0048] The multi-bit counters 530 and 540 are shown as incrementing or decrementing according to active high inputs (as indicated with non-inverted inputs for E/L = 1 = Tate’ and inverted inputs for E/L = 0 = ‘early’). However, similar active low input counters may be used, and the embodiment of FIG. 6 should not be considered limiting.

[0049] It should be noted that early-late difference counter 530 may operate in alternative ways while still maintaining information reflective of the ratio or imbalance of early votes to late votes generated in the time interval. For example, early-late vote difference counter 530 may count only early votes or only late votes. As early-late vote summation counter 540 maintains a count of the total number of early and late votes (i.e., a count of valid transitional data patterns during which valid early-late votes are generated), then the early-late vote measurement for the time interval can be determined by taking the ratio of the number of early votes to the total number of early and late votes (or the number of late votes to the total number of early and late votes).

[0050] Qualified clock edge samples as determined by pattern detection logic 195 are processed by Early/late logic 505, producing pulses corresponding to each early or late phase error detected. As shown, the edge sample candidate Edge _n is compared to the data decision generated in the preceding (i.e., n-1) signaling interval D _n -i to determine if Edge _n is early or late. In some embodiments, other early/late logic 505 may compare the value of Edge _n (0 or 1) to the polarity of the transitional data pattern used to qualify the sample (i.e. whether the trajectory was [1, 0, 0] or [0, 1, 1] ).

[0051] Charge pump 520 receives, at an enabling input, the transitional data pattern verification signal from pattern detection logic 195 and converts the early-late votes into incremental pump- up and pump-down adjustments to the VCO. As mentioned above, an imbalance in the magnitude of pump up and pump down signal from the charge pump may result in the average number of early votes to late votes to be imbalanced.

[0052] As described above, after termination of the respective time intervals, the values of the early-late vote difference counter 530 and, in some cases, the early-late vote summation counter 540, may be transferred to multi-bit registers within CDR-lock detection circuit 570. The CDR- lock detection circuit 570 may include additional logic and processing means (such as an on-chip or off-chip processor configurable and programmable for executing various calculations of stored data) for calculating and comparing the first and second early-late vote measurements generated in the first and second time intervals. Furthermore, incrementing frequency counter 550 clocked by a data rate clock (or fractional division derived from that clock) during that measurement interval allows the data rate frequency to be measured as well.

[0053] In a first embodiment, the first and second time intervals may be defined by a predetermined number of consecutive signaling intervals in the data stream. In such embodiments, the total number of early and late votes generated in the first and second time intervals may be different, and thus CDR-lock detection circuit 570 may normalize the value of early-late vote difference counter 530. In one particular embodiment, CDR-lock detection circuit 570 normalizes the value of early-late vote difference counter 530 by the total number of early and late votes validated in the time interval e.g., by a division. The result for each of the time intervals may subsequently stored in respective multi-bit registers for subsequent comparison.

[0054] In a second embodiment, the first and second time intervals may be defined by a set of consecutive transitional signaling intervals (i.e., a predetermined number of early and late votes generated over a consecutive portion of the data stream). In such an embodiment, normalization may not be needed as the first and second time intervals will be defined by the same number of early and late votes. In such embodiments, CDR-lock detection circuit 570 may perform a direct comparison of the values generated by early-late vote difference counter 530 in the first and second time intervals. [0055] The CDR-lock detection circuit 570 may include logic including e.g., XOR gates to compare the multi-bit registers containing the first and second early-late vote measurements. In some embodiments, the CDR-lock detection circuit 570 performs a bit-wise comparison of a set of most-significant-bits (MSBs) of the multi-bit registers, where a set of least-significant-bits (LSBs) corresponds to the predetermined threshold. For example, if the first and second early-late vote measurements correspond to 16-bit values, one embodiment may compare the 13 MSBs between the first and second early-late vote measurements, while the 3 LSBs correspond to so- called “don’t cares”, setting the predetermined threshold between the first and second early-late vote measurements.

[0056] This partitioning between hardware and software functions in CDR-lock detection circuit 570 is purely for descriptive convenience, without implying limitation.

[0057] In some embodiments, the system clock may include a spread spectrum clocking (SSC) mode of operation. In such embodiments, the frequency of the data rate clock and the data stream may periodically shift, e.g., on the order of several hundred parts per million (ppm) over the course of e.g., a 33us period (i.e., a modulation frequency of 30-33kHz). Thus, an imbalance between early and late votes generated while the frequency of the data rate clock is shifting may be expected. Such numeric examples should not be considered limiting. In such embodiments, the frequency shift of the data rate clock may be associated with an imbalance between early and late votes generated by early/late logic 510. In some such embodiments, the early-late vote measurements taken e.g., during timer intervals wherein the frequency of the data rate clock is increasing may be similar. In such embodiments, the predetermined threshold may account for discrepancies in the early-late vote measurements generated during time intervals occurring at different frequencies of the data rate clock. Furthermore, if the first time interval occurs while the frequency of the data rate clock is increasing while the second time interval occurs while the frequency of the data rate clock is decreasing, the early-late vote measurements may be different yet related. For example, the first early-to-late vote measurement during the first time interval may deviate from a 50-50 ratio by an amount in a first direction, while the second early-to-late vote measurement during the second time interval may deviate from the 50-50 ratio by the same amount in the opposite direction. In some such embodiments, the first and second early-to-late vote measurements may be compared by determining the percentages above and below 50-50 and comparing them and determining whether or not the comparison is within the predetermined threshold. In other words, the number of early votes to late votes while the frequency of the data rate clock is increasing may be the inverse or reciprocal of the number of early votes to late votes while the frequency of the data rate clock is decreasing.