Clock Distribution Buffer

The present invention relates to a clock distribution buffer for a local oscillator, and in particular a clock distribution buffer which provides efficient power consumption across a wide range of operational frequencies.

In a received system a local oscillator (LO) provides a frequency signal which is beat against an input signal (e.g. from an antenna) by a mixer so as to generate lower frequencies which can be handled by the subsequent amplifier.

Multi-standard radio frequency (RF) devices are necessarily required to operate over a wide range of frequencies. The mixer in such a device requires the LO to operate at a frequency near that of the desired input signal, which can of course vary from low MHz to GHz. The LO is usually generated by a phase locked loop and the clock signal is buffered and routed to the mixer.

To achieve good conversion, the LO clock must have sufficient signal swing to fully drive the mixer. The buffer must provide enough current to achieve the required slew rate in order to drive the capacitive loading presented by the following stage and by the clock routing.

Figure 1 illustrates a high frequency clock 1 and a low frequency clock 3. Clearly, the high frequency clock 1 requires a high slew rate in order to achieve a full signal swing within the period of the signal, whereas the low frequency clock 3 can achieve full signal swing within the period of the signal with a lower slew rate.

To achieve the required clock speeds and slew rates, the clock distribution network can often consume a large amount of current. However, while large amounts of current are required in order to achieve the required slew rates to operate well in the GHz frequency range, such consumption is unnecessarily large for low MHz frequencies. Therefore at low frequencies such systems can be inefficient.

It is therefore an object of the present invention to provide efficient power consumption across a wide range of operational frequencies of a local oscillator.

According to a first aspect of the present invention, there is provided a buffer for a switched current circuit, the buffer comprising a resistive load and a bias current source, wherein one or both of the resistive load and the bias current source are controllable so as to vary the slew rate of the buffer.

The buffer may be used for driving a mixer, and may be employed as one of a chain of buffers, and is also suitable for latches, dividers or converters. The controllable nature of the resistive load and bias current source enables the slew rate of the buffer to be tailored to the operational frequency desired so as to reduce unnecessary power consumption.

Preferably, the buffer comprises a control means configured so as to control one or both of the resistive load and bias current source dependent on a desired operational frequency.

Preferably, the control means reduces a resistance of the resistive load when the desired operational frequency increases. Preferably or alternatively, the control means increases a bias current provided by the bias current source when the desired operational frequency increases.

Preferably, the control means increases a resistance of the resistive load when the desired operational frequency decreases. Preferably or alternatively, the control means decreases a bias current provided by the bias current source when the desired operational frequency decreases.

Controlling the resistance of the load and/or the current dependent on the frequency of interest has a number of advantages, primarily stemming from the resulting effect on the slew rate. Primarily, at low frequencies where slower slew rates can be tolerated, current consumption

can be reduced by not placing the same demands on the system as for a higher frequency which requires a faster slew rate and hence higher current.

Preferably, the resistive load comprises an array of selectable resistances. Preferably, one or more of the selectable resistances are selectable by activating one or more corresponding switches. Preferably, the switches are controlled by the control means. Preferably, the selectable resistances each comprise a fixed resistance.

Alternatively, the resistive load comprises a substantially continuously variable resistance. Preferably, the variable resistance is controlled by the control means.

Optionally, the resistive load may comprise a plurality of arrays of selectable resistances. Preferably, selective actuation of one or more of the plurality of arrays allows an output voltage of the buffer to be varied. Preferably, the control means is configured to selectively actuate one or more of the plurality of arrays.

Preferably, the bias current source is a variable current source. Preferably, the bias current source is controlled by the control means so as to control the bias current.

Preferably, the bias current source comprises a substantially continuously variable current source.

Alternatively, the bias current source comprises an array of selectable current sources. Preferably, one or more of the selectable current sources are selectable by activating one or more corresponding switches . Preferably, the switches are controlled by the control means. Preferably, the selectable current sources each comprise a fixed current source.

Optionally, the control means comprises a controller.

Preferably, the controller is a microprocessor, DSP or FPGA.

Optionally, the controller comprises program instructions which when executed effect control of one or both of the resistive load and the bias current source. Preferably, the program instructions effect control of one or both of the resistive load and the bias current source responsive to the desired operational frequency or measured slew rate.

According to a second aspect of the present invention, there is provided a local oscillator circuit for driving a mixer in a tuning system, the local oscillator circuit comprising a clock pulse generator and one or more buffers according to the first aspect.

Most preferably, at least one of said buffers is located subsequent to the clock pulse generator so as to receive generated clock pulses. Preferably, the clock pulse generator comprises a phase locked loop.

Optionally, the local oscillator circuit further comprises a divider circuit, adapted to convert the generated clock pulses from a first frequency to a second frequency. Most preferably, the divider circuit is located subsequent to the clock pulse generator and at least one of said buffers. Optionally, a further of said buffers is located subsequent to the divider circuit and prior to the mixer.

The present invention will now be described by way of example only and with reference to the accompanying figures in which:

Figure 1 illustrates a high frequency clock and a low frequency clock and the respective slew rate requirements;

Figure 2 illustrates in schematic form a prior art switched current logic clock buffer;

Figure 3 illustrates in schematic form a half circuit diagram of the switched current logic buffer during (a) discharging and (b) charging;

Figure 4 illustrates in schematic form a switched current logic clock buffer in accordance with an aspect of the present invention;

Figure 5 illustrates in schematic form a local oscillator system comprising a number of buffers as described with reference to Figure 4;

Figure 6 illustrates in schematic form a switched current logic latch according to the present invention; and

Figure 7 illustrates in schematic form a switched current logic driver circuit also according to the present invention.

Figure 2 illustrates a switched current logic (SCL) clock buffer 5 as known in the art. SCL is commonly used in delivering high frequency clocks, and implementing SCL in such a clock buffer allows high slew rates and good supply rejection. Figure 3 (a) and 3 (b) show (half circuit) diagrams explaining the operation of the SCL clock buffer 5 in the discharging state (a) and the charging state (b) - corresponding to the trailing edge 7 and leading edge 9 (respectively) of clock pulses at the drain of transistor 11.

In Fig.3 (a) the positive clock input 13 (see Fig.2) to the base of transistor 11 is high, thus permitting current flow (in the direction indicated by the arrows) resulting in a drop in the output voltage. The full voltage swing is equivalent to the bias current I _b i _as (provided by current source 15) multiplied by the resistance R of the load resistor 17. The slew rate is determined by Ibias/ ^R and the load capacitance Ci _oa d- In Fig.3(b), the positive clock input 13 is low and hence transistor 11 is switched off. The output voltage is therefore charged to the level of the supply voltage through load resistor 17. In this case the slew rate is determined by the RC time constant of R and Ci _oa d- A lower resistance will therefore result in faster charging.

With reference to Figure 4, there is presented an improved SCL clock buffer 101 that comprises a programmable load 103 and a programmable current source 105. Similarly to the prior art buffer 5, this buffer comprises a positive clock input 113 and a negative clock input 114, each of which feed respective transistors 111 and 112.

Programmable load 103 comprises an array of resistances 117i...n and 118i...n, each of which may be introduced (alone or in combination with other resistances) by actuation of one or more of corresponding switches 119i...n and 12Oi...n . Again, taking the positive clock input side to exemplify the invention, when the positive clock input 113 is high (the negative clock input 114 being low and hence transistor 112 in an "off" state) the full voltage swing is equivalent to the bias current I _pr og (provided by programmable current source 105) multiplied by the resistance R of the switched-in load resistance (s) 117i...n. The slew rate is determined by I _pro g, the switched in load resistance (s) and the load capacitance. As the load and the bias current are programmable, the slew rate can therefore be optimised dependent on the desired frequency of operation.

Adjusting the bias current and the resistance allows a consistence voltage swing to be achieved across the range of frequencies of interest. For example, when the frequency of interest is in the, say, GHz region the bias current will be set to a high value and the load set to a low resistance value. Conversely, when the frequency of interest is in the Mhz region (for example) the bias

current will be lowered and the load set to a high value of resistance. This allows an appropriate slew rate to be achieved across a wide range of frequencies without requiring the same level of current consumption when operating in the lower frequency regions.

The programmable nature of the load and bias current is readily controllable to achieve the desired slew rates because the frequency of interest will always be known. The number n and value of the selectable resistances 117i...n and 118i...n, and the current range over which the bias current source can operate, can be selected by the designer of such a system dependent on the level of optimisation required. For example, more selectable resistances mean greater resolution and more specific tailoring to the various frequencies which may be of interest. However, there is a direct relationship between the number of selectable resistances and the size of the corresponding circuit, so there is a trade-off between the tuning resolution and real estate. Furthermore, added complexity increases the likelihood of faults, so this must also be taken into consideration.

It is also foreseen that a feedback loop could be employed to monitor the slew rate and adjust system parameters in response to the monitored slew rate to compensate for process and performance variations.

The buffer 101 may be employed in various stages of a multi-standard system for power optimisation. Figure 5 illustrates in schematic form the typical blocks used for local oscillator generation which drives a mixer. A phase-locked loop (Frac-N PLL) generates a train of clock

pulses which drive a first buffer 101 which optimises power consumption dependent on the clock frequency. The clock frequency is then divided by a programmable divider so as to generate a lower frequency clock pulse train, which is fed into a second buffer 102 which again optimises power consumption dependent on the new clock frequency (which has been down-converted by the programmable divider) . This buffered signal then drives the mixer so as to mix down the RF input to the desired frequency. Using the buffer at a number of stages in this way means that power consumption can be optimised throughout a system.

As mentioned above, the programmable bias and load can be utilised in other SCL systems. Figure 6 illustrates a latch or flip-flop 201 incorporating such programmable elements; programmable bias 205 and programmable load 203 (corresponding to bias 105 and load 103 in Figure 4) . Such a latch can be used in a programmable divider which would allow power consumption to be optimised by tailoring the slew rate dependent on the clock frequency.

Similarly to the SCL clock buffer 101 above, the SCL latch 201 comprises a programmable current source 205 which provides a controllable bias current, and an array of load resistances 217i...n, 218i...n . These resistances are selectable by corresponding arrays of switches 219i...n, 220i...n which allow control of the load resistance for both the positive and negative halves of the latch circuit (respectively) . The number and nature of resistances n can be tailored to suit a particular application.

Figure 7 shows an alternative SCL system 301 employing the programmable nature of the present invention. In this case, the SCL system is a driver circuit which can switch between two fixed levels by incorporating an additional programmable load. The load is selectively switched in (or alternatively switched between additional load resistances) so as to alter the voltage level at the positive/negative output. So in this case not only can the SCL circuit be optimised in terms of power consumption by tailoring the slew rate dependent on the operational frequency, but the output voltage can also be varied dependent on whether and which of the additional programmable resistances are switched in.

In summary, the present invention allows optimised power consumption in switched current logic circuits by tailoring the slew rate of the system such that at lower frequencies (where lower slew rates can be tolerated) power consumption is scaled down, while allowing power consumption to be scaled up to allow higher slew rates for higher frequency operation.

Further modifications and improvements may be added without departing from the scope of the invention as defined by the appended claims. For example, although the invention has been described as being applicable to a buffer for driving a mixer, the technique can be used for any switched current logic circuits operating across a range of frequencies, e.g. a chain of buffers, latches, dividers or converters.