Title:
CLOCK DIVISION CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD
Document Type and Number:
WIPO Patent Application WO/2010/050098
Kind Code:
A1
Abstract:
A clock division circuit (11) masks (S – N) clock pulses among S clock pulses of an input clock signal according to a division ratio defined by an N/S and generates an output clock signal obtained by N/S-dividing the input clock signal. The clock division circuit (11) includes a mask control circuit (40) and a mask circuit (50). The mask control circuit (40) generates a mask signal by allocating a non-mask timing with a higher priority, to clock pulses at the timings where no clock pulse exists in the clock signal used by a circuit Ai other than a target circuit Bi using the output clock signal among the S clocks of the input clock signal. The mask circuit (50) masks the clock pulse of the input clock signal in accordance with the mask signal generated by the mask control circuit so as to generate an output clock signal.
Inventors:
SHIBAYAMA, Atsufumi (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
Application Number:
JP2009/003633
Publication Date:
May 06, 2010
Filing Date:
July 30, 2009
Export Citation:
Assignee:
NEC Corporation (7-1 Shiba 5-chome, Minato-ku Tokyo, 01, 〒1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 〒1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 〒1088001, JP)
International Classes:
H03K23/64; G06F1/04; G06F1/08; G06F1/10; H03K5/15
Attorney, Agent or Firm:
IEIRI, Takeshi (HIBIKI IP Law Firm, Asahi Bldg. 10th Floor 3-33-8, Tsuruya-cho, Kanagawa-ku, Yokohama-sh, Kanagawa 35, 〒2210835, JP)
Download PDF: