Title:
CLOCK DIVISION CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD
Document Type and Number:
WIPO Patent Application WO/2010/050098
Kind Code:
A1
Abstract:
A clock division circuit (11) masks (S – N) clock pulses among S clock pulses of an input clock signal according to a division ratio defined by an N/S and generates an output clock signal obtained by N/S-dividing the input clock signal. The clock division circuit (11) includes a mask control circuit (40) and a mask circuit (50). The mask control circuit (40) generates a mask signal by allocating a non-mask timing with a higher priority, to clock pulses at the timings where no clock pulse exists in the clock signal used by a circuit Ai other than a target circuit Bi using the output clock signal among the S clocks of the input clock signal. The mask circuit (50) masks the clock pulse of the input clock signal in accordance with the mask signal generated by the mask control circuit so as to generate an output clock signal.
Inventors:
SHIBAYAMA ATSUFUMI (JP)
Application Number:
PCT/JP2009/003633
Publication Date:
May 06, 2010
Filing Date:
July 30, 2009
Export Citation:
Assignee:
NEC CORP (JP)
SHIBAYAMA ATSUFUMI (JP)
SHIBAYAMA ATSUFUMI (JP)
International Classes:
H03K23/64; G06F1/04; G06F1/08; G06F1/10; H03K5/15
Foreign References:
| JP2006245631A | 2006-09-14 | |||
| JP2001127618A | 2001-05-11 |
Attorney, Agent or Firm:
IEIRI, Takeshi (JP)
家入健 (JP)
家入健 (JP)
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