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Title:
CLOCK FREQUENCY DIVIDER CIRCUIT AND CLOCK FREQUENCY DIVIDING METHOD
Document Type and Number:
WIPO Patent Application WO/2010/070830
Kind Code:
A1
Abstract:
A clock frequency divider circuit for generating a clock signal that allows an expected correct communication operation to be performed in communication with a circuit that operates on a clock having a different frequency.  The clock frequency divider circuit comprises a mask control circuit (20) and a masking circuit (10).  The mask control circuit (20) comprises: a mask timing signal generating circuit (22) that generates, based on communication timing signals (26), mask timing signals (29) for masking, on a priority basis, those ones of M clock pulses of an input clock signal which are other than the clock pulses occurring at communication timings; and a mask suppressing circuit (62) that suppresses the masking of the clock pulses at the communication timings.  The masking circuit (10) masks, in response to a mask signal (50) generated by the mask control circuit, the clock pulses of the input clock signal to generate an output clock signal.

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Inventors:
SHIBAYAMA, Atsufumi (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
Application Number:
JP2009/006557
Publication Date:
June 24, 2010
Filing Date:
December 02, 2009
Export Citation:
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Assignee:
NEC Corporation (7-1 Shiba 5-chome, Minato-ku Tokyo, 01, 〒1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目7番1号 Tokyo, 〒1088001, JP)
International Classes:
H03K23/64; G06F1/08; H03K21/00; H03K21/40
Foreign References:
JPS6382015A
JPS637016A
JPH0946222A
JPS63151217A
Attorney, Agent or Firm:
IEIRI, Takeshi (HIBIKI IP Law Firm, Asahi Bldg. 10th Floor 3-33-8, Tsuruya-cho, Kanagawa-ku, Yokohama-sh, Kanagawa 35, 〒2210835, JP)
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