Title:
CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME
Document Type and Number:
WIPO Patent Application WO/2016/114892
Kind Code:
A3
Abstract:
A CGC includes an enable module (302) and a latch module (306). The enable module (302) has an enable module input and an enable module output. The latch module (306) has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module (306) is configured to enable and to disable the clock (clk_in) via the latch module output based on the enable module input. The latch module (306) includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output, the internal enable node and the clock.
Inventors:
RASOULI SEID HADI (US)
DILLEN STEVEN JAMES (US)
DATTA ANIMESH (US)
DILLEN STEVEN JAMES (US)
DATTA ANIMESH (US)
Application Number:
PCT/US2015/066116
Publication Date:
September 01, 2016
Filing Date:
December 16, 2015
Export Citation:
Assignee:
QUALCOMM INC (US)
International Classes:
H03K19/00
Domestic Patent References:
| WO2014043856A1 | 2014-03-27 |
Foreign References:
| US20120299622A1 | 2012-11-29 | |||
| US20140070847A1 | 2014-03-13 | |||
| US7825689B1 | 2010-11-02 | |||
| US20100109747A1 | 2010-05-06 |
Attorney, Agent or Firm:
GELFOUND, Craig A. et al. (1717 K Street NWWashington, District of Columbia, US)
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