Title:
CLOCK GENERATION CIRCUIT AND INTEGRATED CIRCUIT FOR REPRODUCING AN AUDIO SIGNAL COMPRISING SUCH A CLOCK GENERATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO2002043245
Kind Code:
A3
Abstract:
A clock generation circuit (30) according to the invention comprises a frequency divider (46) for generating a first intermediate clock signal (CLa) from an input clock signal. A first logical unit (47) combines the input clock signal (CLin) and the intermediate clock signal (CLa). The circuit (30) further comprises a clocked bistable unit (48) having a clock input coupled to an output of the first logical unit (47), and a data input and a data output, and a second logical unit (49) having a selection input for receiving a synchronization signal (SorR) from a synchronization module (51) having an input (7a) for receiving a reference clock signal (CL1). The synchronization signal controls selection between a feedback mode and a reset mode. In the feedback mode the second logical unit (49) logically inversely couples the data input to the data output, and in the reset mode the second logical unit (49) provides a reset value to the data input. The data output provides the output clock signal (CLout). The clock generation circuit according to the invention is in particularly suitable for a device for reading/writing information from/to an information carrier (1).
Inventors:
DE CUYPER STEVEN H
Application Number:
PCT/EP2001/013335
Publication Date:
November 14, 2002
Filing Date:
November 15, 2001
Export Citation:
Assignee:
KONINKL PHILIPS ELECTRONICS NV (NL)
International Classes:
G06F1/08; G11B20/14; H03L7/00; (IPC1-7): H03L7/00; H03K5/156; G06F1/08
Foreign References:
| US5365119A | 1994-11-15 | |||
| US5636249A | 1997-06-03 |
Download PDF: