Title:
CLOCK GENERATION CIRCUIT FOR SUCCESSIVE APPROXIMATION A/D CONVERTER
Document Type and Number:
WIPO Patent Application WO/2011/121683
Kind Code:
A1
Abstract:
A clock generation unit (11) causes a clock (SCK) to transition to a second voltage level when a clock (RCK) transitions to a first voltage level, and causes the clock (SCK) to transition to the first voltage level when the transition of a clock (ICK) from the first voltage level to the second voltage level has occurred n times. A clock generation unit (12) causes the clock (ICK) to transition to the first voltage level when the clock (SCK) transitions to the second voltage level, causes the clock (ICK) to transition to the second voltage level when comparison signals (QP, QN) transition to mutually different voltage levels, and causes the clock (ICK) to transition to the first voltage level following the elapse of a variable delay time when the comparison signals (QP, QN) transition to the same voltage level. A delay control unit (13) controls the variable delay time of the clock generation unit (12) in a manner such that the proportion of the first voltage level period of the clock (SCK) relative to the cycle of the clock (RCK) approaches a predetermined proportion.
Inventors:
SAKIYAMA SHIRO
MATSUMOTO AKINORI
TOKUNAGA YUSUKE
KUWABARA ICHIRO
MATSUMOTO AKINORI
TOKUNAGA YUSUKE
KUWABARA ICHIRO
Application Number:
PCT/JP2010/006065
Publication Date:
October 06, 2011
Filing Date:
October 13, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
SAKIYAMA SHIRO
MATSUMOTO AKINORI
TOKUNAGA YUSUKE
KUWABARA ICHIRO
SAKIYAMA SHIRO
MATSUMOTO AKINORI
TOKUNAGA YUSUKE
KUWABARA ICHIRO
International Classes:
H03M1/38
Domestic Patent References:
| WO2008026440A1 | 2008-03-06 |
Foreign References:
| JP2000295106A | 2000-10-20 | |||
| JPH0837461A | 1996-02-06 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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Claims:
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