Title:
CLOCK GENERATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/211979
Kind Code:
A1
Abstract:
The present invention reduces jitter superimposed on a clock signal. This clock generation circuit is provided with: a mode-locked laser 1 that generates an optical pulse; a photodiode 2 that performs photoelectric conversion of the optical pulse generated by the mode-locked laser 1; and a filter 3 that attenuates at least one of a high-frequency component and a DC component of the mode-locked laser 1 included in an electrical signal output from the photodiode 2.
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| JPS58195314 | PULSE TRANSMITTER |
Inventors:
TANAKA KENJI (JP)
MIURA NAOKI (JP)
NAKANO SHINSUKE (JP)
NOSAKA HIDEYUKI (JP)
MIURA NAOKI (JP)
NAKANO SHINSUKE (JP)
NOSAKA HIDEYUKI (JP)
Application Number:
PCT/JP2019/016460
Publication Date:
November 07, 2019
Filing Date:
April 17, 2019
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H03K3/42
Foreign References:
| JP2007251365A | 2007-09-27 | |||
| JP2004282693A | 2004-10-07 | |||
| JPH09233030A | 1997-09-05 | |||
| JPH098741A | 1997-01-10 |
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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