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Title:
CLOCK GENERATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/211979
Kind Code:
A1
Abstract:
The present invention reduces jitter superimposed on a clock signal. This clock generation circuit is provided with: a mode-locked laser 1 that generates an optical pulse; a photodiode 2 that performs photoelectric conversion of the optical pulse generated by the mode-locked laser 1; and a filter 3 that attenuates at least one of a high-frequency component and a DC component of the mode-locked laser 1 included in an electrical signal output from the photodiode 2.

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Inventors:
TANAKA, Kenji (9-11 Midori-cho 3-chome, Musashino-sh, Tokyo 85, 〒1808585, JP)
MIURA, Naoki (9-11 Midori-cho 3-chome, Musashino-sh, Tokyo 85, 〒1808585, JP)
NAKANO, Shinsuke (9-11 Midori-cho 3-chome, Musashino-sh, Tokyo 85, 〒1808585, JP)
NOSAKA, Hideyuki (9-11 Midori-cho 3-chome, Musashino-sh, Tokyo 85, 〒1808585, JP)
Application Number:
JP2019/016460
Publication Date:
November 07, 2019
Filing Date:
April 17, 2019
Export Citation:
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Assignee:
NIPPON TELEGRAPH AND TELEPHONE CORPORATION (5-1 Otemachi 1-chome, Chiyoda-ku Tokyo, 16, 〒1008116, JP)
International Classes:
H03K3/42
Foreign References:
JP2007251365A2007-09-27
JP2004282693A2004-10-07
JPH09233030A1997-09-05
JPH098741A1997-01-10
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (4th Floor Sanno Park Tower, 11-1, Nagatacho 2-chome, Chiyoda-k, Tokyo 04, 〒1006104, JP)
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