Title:
CLOCK OUTPUT METHOD AND APPARATUS
Document Type and Number:
WIPO Patent Application WO/2016/184018
Kind Code:
A1
Abstract:
The present invention provides a clock output method and apparatus. The method comprises: a digital phase-locked loop (DPLL) receives an output recovery clock, wherein the DPLL is configured by using a logical resource of a chip; and the DPLL outputs a clock according to a state of the DPLL. The present invention solves the problems of high device cost and complex design of a printed circuit board (PCB) in the related art, thereby achieving the effect of reducing the device cost and the design complexity of the PCB.
Inventors:
HE BO (CN)
Application Number:
PCT/CN2015/092033
Publication Date:
November 24, 2016
Filing Date:
October 15, 2015
Export Citation:
Assignee:
ZTE CORP (CN)
International Classes:
H04L7/033
Foreign References:
| CN1867119A | 2006-11-22 | |||
| CN2831617Y | 2006-10-25 | |||
| CN1325186A | 2001-12-05 | |||
| EP1351418A2 | 2003-10-08 |
Attorney, Agent or Firm:
KANGXIN PARTNERS, P.C. (CN)
北京康信知识产权代理有限责任公司 (CN)
北京康信知识产权代理有限责任公司 (CN)
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