Field of the Invention

The invention relates generally to matching data rates with independent clock sources across networks and

1 0 more specifically to matching data rates with independent clock sources by adding or deleting entire bits in response to clock underspeed or overspeed conditions.

1 5 Background of the Invention

Current methods of matching data rates between networks with independent clock sources are designed to operate in a nearly error free environment. One such

20 method is that described in CCITT Blue Book

Recommendations V.l lO, (1988) which may make clock compensations in fractions of bit times. Since the V.l lO frame is comprised of 80 total bits, 48 of which are data bits, if the user clock rate is 4.8 Kb/s then each of the 48 25 data bits in the V.l lO frame are used. If, however, the user data rate is 2.4 Kb/s or 1.2 Kb/s, only 1/2 and 1/4 respectively of the 48 data bits in the V. l lO frame are used. In this case, 1/2 and 3/4 of the data bits in the V.l lO frame go unused and are eventually redundantly

3 0 coded. In addition to data bits, clock rate information is also transmitted in the V. l lO frame along with network independent clock adjustment information. In error free systems, this information is passed along from one clock

source to another so that the independent data source can determine the amount of compensation required to accurately convey data.

The above described method is well suited for integrated services digital network (ISDN) environments where typical bit error rates (BER) are in the order of 10" ⁹ . However, when used in a digital radiotelephone environment, for example the Groupe Special Mobile or GSM digital radiotelephone system environment, the method is subjected to typical BER's on the order of 10 ^-3 to 10" ⁵ . The implementation of clock rate matching as described by CCITT Recommendations V.l lO, when used in the GSM environment, causes several problems. First, the method as recommended by the CCITT uses fractions of bit times depending on the data rate to perform clock compensation, however this information is not maintained by the GSM air interface specification which essentially compresses and optimizes the V.l lO frame for over-the-air transmission. The lower fractional data rates are lost in the optimization. Second, errors introduced at the GSM air interface may cause the GSM data services to arbitrarily add or delete bits from the user data stream in the V.l lO frame. If this occurs, not only are data errors incurred, but also the total number of data bits is disturbed due to corruption of the clock compensation mechanism described in CCITT Recommendation V.l lO. This problem itself may render certain types of error correcting protocols useless in the GSM environment.

Another shortcoming of the V.l lO method of matching user data clock speeds is the requirement of a sampling mechanism to monitor the phase difference between the two clocks in the independent clocks. In order to achieve the required resolution, the clocks should be

oversampled in order to measure the required phase difference. This requirement adds an extra and expensive overhead to the GSM data support platform and adds eight complex phase states necessary to implement the compensation mechanism.

Thus, a need exists for a method of matching user data rates with independent clock sources across networks in a high BER environment and also does not require expensive, real-time intensive, and complex additions to the data support platform.

Summary of the Invention

A communication system interfaces with a network having data clocked at different rates. The communication system has a transmitter and a receiver which convey data rate compensation information, where the receiver is directed to compensate for the data rate difference by fractions of bits. The communication system is characterized in that the receiver receives the data rate compensation information and, in response thereto, compensates for the data rate difference by an integer multiple of bits.

Detailed Description of the Drawings

FIG. 1 generally depicts a radiotelephone system which may incorporate the present invention.

FIG. 2 depicts the structure of a V.l l O frame as defined by CCITT recommendation V. l lO.

FIG. 3 depicts two successive V.l lO frames forming a multi-frame in accordance with the invention.

FIG. 4 generally illustrates an apparatus which performs independent clock rate matching in a transmitter in accordance with the invention.

FIG. 5 generally illustrates an apparatus which performs independent clock rate matching in a receiver in accordance with the invention.

FIG. 6 generally illustrates in flow diagram form the steps the IWF undergoes to match independent clock rates and transmit data in accordance with the invention.

FIG. 7 generally illustrates in flow diagram form the steps the IWF undergoes to match independent clock rates and receive data in accordance with the invention. FIG. 8 generally illustrates in flow diagram form the steps a communication system undergoes to convey data from one network having independent clock sources to another network having independent clock sources in accordance with the invention.

Detailed Description of a Preferred Embodiment

FIG. 1 generally depicts a communication or radiotelephone system which may incorporate the present invention. A public switched telephone network

(PSTN)/integrated services digital network (ISDN) 100 is coupled to a mobile network (MN) 106. The PSTN/ISDN 100 is generally comprised of the land-line telephone system and computers or other data transfer hardware which might require modems to transmit data. A modem data call in the radiotelephone system of FIG. 1 is accomplished as follows. An originator in the PSTN 100

initiates a call to the mobile switching center (MSC) 105 in the MN 106. The call is sent to the MSC 105 in the form of audio where it is routed to a data interface or an interworking function (IWF) 125. The IWF 125 converts the audio format of the data coming from the PSTN 100 to a digital format (ISDN like) in the MN 106. The digital data is processed into a data transfer frame or V.l lO frame format which is a standard rate adaptation frame used in the MN 106. The V.l lO frame then enters a base-station system (BSS) 115 where it is further processed into a standard air interface format as specified in GSM Recommendation 4.21, version 3.2.0, March 1990. The data contained in the GSM air interface frame is transmitted over an antenna 120. A mobile 110 receives the air interface frame containing the data and processes (not shown) the data back to the V.l lO format.

In the system shown in FIG. 1 , the PSTN/ISDN 100 is not required to be synchronized to the MN 106. If it is synchronized, the corresponding clock signals that drive the modem 126 in the IWF 125 are synchronized to the rate adaptation block 127 in the IWF 125. Consequently, clock matching between the modem 126 and the rate adaptation block 127 is not required. If, however, the two networks are not synchronized, the clock driving the modem 126 will not be matched to the clock used in the rate adaptation block 127. For non-radiotelephone applications, the CCITT recommendation for the V. l lO framing provides a mechanism to compensate for the problem of mis-matched clocks. The procedure, depending upon the data rate involved, adds or deletes full bits, 1/2 bits and 1/4 bits of the V.l lO frame as required to speed up or slow down the data rate.

FIG. 2 depicts the structure of a V.l lO frame as defined in the CCITT recommendation V.100. The V.l lO frame is comprised of 10 octets, each octet having 8 bits.

Octet 0 is comprised of 8 "0" bits and is used for synchronization purposes. The first bit of every subsequent octet is a "1 " bit and again is used for synchronization purposes. The remaining bits in the V.l lO frame are comprised of three types of bits. D bits carry the user data stream, S and X bits carry the modem status signals, and E bits carry the user data rate and clock compensation information. In the preferred embodiment, the E bits, specifically E4, E5, E6, and E7 are modified in the inventive clock compensation procedure. FIG. 3 generally depicts a first V.llO frame 300 and a second V.l lO frame 305 transmitted to form a multi-frame 310, which is the implementation in the preferred embodiment. The use of four E bits from each of the two V.l lO frames forms an 8 bit code word that is forward error corrected (FEC) encoded. Thus, 2 of the 8 E bits are used to represent the clock compensation states while the remaining 6 E bits are used to forward error correct the multi-frame.

Since the air interface uses a smaller bandwidth than the V.llO frame, some of the bits in the V.llO frame must be discarded and/or compressed. If the compensation mechanism stated in the CCITT recommendation V.l lO were to be used, the added or deleted 1/2 or 1/4 bits would be lost in the removal and compression of bits at the base-station system (BSS) 115 of the MN 106. In addition to the mapping problem between the air interface and the V.l lO frames, the high BER could cause false addition or deletion of data bits. This falsing changes the number of transmitted data bits consequently leading to severe data errors.

FIG. 4 generally depicts the hardware that performs clock error rate matching in accordance with the invention. A pulse code modulated (PCM) signal which is typically used for audio communications in digital trunks or links, is input into an analog/PCM block 124. The PCM line contains samples of the audio and the clock, CLK1, of the PSTN 100. The clock information, labeled CLK1, is extracted by the modem 126. The user data enters the modem from the analog PCM block 124 where it is re-formatted to its raw data form. The CLK1 signal is used to clock the raw data, symbolized by the DAT line exiting the modem 126. At this point, the DAT line contains data which is being transmitted at a first clock rate or CLK1. The data exiting the modem 126 is input into a data buffer 400 which resides in the rate adaptation block 127. The data is clocked into the buffer 400 by a second clock rate, CLK2 which is derived from the MSC 105. The data buffer 400 accepts the data from the DAT line. At this point, the clock difference between CLK1 and CLK2 is determined. This determination is accomplished by setting pointers in the data buffer 400. For example, one pointer measures the rate at which data bits enter the data buffer 400, which would be at the rate of CLK1, and a second pointer measures the rate of data exiting the data buffer 400, which would be the rate of CLK2 clocking data out of the buffer 400. If CLK1 is less than CLK2 by a lower threshold, a clock underspeed condition occurs. In this condition, data on the DAT line entering the buffer is entering the data buffer 400 slower than data is exiting the data buffer 400. To match the two clock rates, the data exiting the data buffer 400 will have an entire bit deleted when the clock underspeed falls below a lower threshold. Likewise, if CLK1 is greater than CLK2 by an upper threshold, a clock

overspeed condition occurs whereby data is entering the data buffer 400 faster than data is exiting the data buffer 400. In this condition, the rate of data exiting the data buffer 400 must increase, thus an entire bit is added to the data exiting the buffer 400. This insertion occurs when the clock overspeed or the difference in the two clock rates exceeds an upper threshold. If the difference between CLK1 and CLK2 is not above or below the upper or lower threshold, the data exiting the buffer 400 is not altered.

Four clock compensation states are possible in the preferred embodiment and are depicted in Table 1 for illustrative purposes only; the state versus bit pattern may change depending on the system design.

Table 1

Table 1 generally depicts the clock compensation states and their corresponding function and bit pattern, and again is only for illustrative purposes. In the case where the two clocks are essentially equivalent, no change is required in the data bits exiting the buffer 400, so state 1 representing no change might correspond to a bit pattern of "00". For a clock underspeed condition, where the requirement is to delete one bit, a second state, or state 2 might be

represented by a bit pattern of "01 ". For clock overspeed, 2 separate states are necessary since the clock overspeed condition requires that a bit be inserted into the exiting data bits; the inserted bit may either be a "0" or " 1". State 3 then corresponds to inserting a "0" bit and might be represented by a bit pattern of " 10" while state 4 corresponds to inserting a bit "1 " and might be represented by a bit pattern of "11 ". Hysteresis capability can be added by setting two thresholds for each pointer, depending on the state of the compensation.

The determination of the proper clock compensation state is accomplished by a digital signal processor (DSP) 406 and a microprocessor (μP) 405, which in the preferred embodiment are a Motorola 56001 DSP and a Motorola 68020 μP. The μP monitors the pointers in the buffer 400 and determines the appropriate state and representative bit pattern by comparing the rate at which data enters the buffer 400 to the rate at which data exits the buffer 400. As the μP 405 receives data from the modem 126, the μP 405 formats the data into a V.l lO frame. Once the required compensation state has been determined, the DSP 406 alters the number of data bits in the multi-frame 310 accordingly. If the μP 405 determines that no change is necessary, a bit pattern of "00" is used as a compensation state, and no alteration of the number of data bits D in the multi-frame occurs. If the μP 405 determines a clock underspeed is present, i.e. state 2, a bit pattern of "01 " is inserted into two of the eight E bits in the multi-frame 310. In this case, the terminal receiving the multi-frame 310 will ignore the data bit immediately following the E bits of the second V.l lO frame 305. If the μP 405 determines that the number of data bits in the multi-frame 310 needs to be increased by a bit, the μP 405 will increase the

number by adding a "0" or "1" bit in the total user data bits. This occurs between the last data bit preceding the E bits and the first data bit following the E bits in the second V.l lO frame. The IWF 125 is a duplex system, thus it also receives

V.l lO frames that have been transmitted and altered. FIG. 5 depicts the receiving and transformation process from the V.l lO frame to the raw data as required as input by the modem 126. A data receiver 500 receives the multi- frame 310 which again is comprised of a first V.l lO frame 300 and a second V.l lO frame 305. The frames are input into a DSP 506 and a μP 505, which again in the preferred embodiment are a Motorola 56001 DSP and a Motorola 68020 μP. The μP 505 and the DSP 506 are clocked by CLK2 which is derived from the MN 106 clock. Depending on the compensation state received, the DSP 506 decodes the forward error correction that was performed on the compensation state bits, and sends the decoded state to the μP 505 where the data bits of the multi-frame 310 are altered accordingly. For example, if the compensation state is state 2, the microprocessor will ignore the data bit immediately following the E bits of the second V.l lO frame 305. If the decoded state is such that a state 3 or state 4 condition is present, the microprocessor will add a bit in to the raw data bits exiting the microprocessor 505. Output from the microprocessor 505 is input into a data buffer 500 which again has a clock input of CLK2. By invoking the correct compensation, the μP 505 creates the new rate for the modem 126 which has data clocked into it at CLK1. The data is conveyed to the analog/PCM block 124 where it is converted to a PCM signal and conveyed back to the MSC 105. At this point, referring to FIG. 1, the MSC 105

transmits the data to the PSTN/ISDN networks 100 in a audio modulation format using PCM samples.

FIG. 6 generally illustrates in flow diagram form the steps the IWF undergoes to match independent clock rates and transmit data in accordance with the invention. The process in the IWF starts at 600 by providing at 603 a clock having a second clock rate and accepting at 606 at least a predetermined number of network information bits and data bits at a first clock rate. The μ P 405 then determines at 609 the difference between the first clock rate and the second clock rate. The DSP 406 alters at 612 the predetermined number of data bits by an integer multiple of bits and the data transmitter 420 transmits at 615 at least one network information bit and at least the altered data bits at the second clock rate.

FIG. 7 generally illustrates in flow diagram form the steps the IWF undergoes to match independent clock rates and receive data in accordance with the invention. The process in the IWF starts at 700 when a data receiver 500 receives at 703 at least one data transfer frame at a second clock rate. The DSP 506 determines at 706 the clock compensation state, the μP 505 alters at 709 the number of data bits by at least one data bit and the clock adjustment block 501 adjusts at 712 the second clock rate to match the clock rate of the destination network.

FIG. 8 generally illustrates in flow diagram form the steps a communication system undergoes to convey data from one network having independent clock sources to another network having independent clock sources in accordance with the invention. The process starts at 800 when the first data interface provides at 803 a second clock having a second clock rate. The first data interface then accepts at 806 at least a predetermined number of

network information bits and data bits at a first clock rate and determines at 809 the difference between the first and second clock rate. The first data interface then alters at 812 the predetermined number of data bits by at least one data bit and transmits at 815 at least one network information bit and at least the altered data bits at the second clock rate. The second data interface then receives at 818 at least one network information bit and at least the altered data bits at the second clock rate and determines at 821 the clock compensation state. The second data interface then alters at 824 the number of data bits by at least one data bit and adjusts at 827 the second clock rate to match the clock rate of the destination network.

Not only is this procedure for clock matching of independent clock sources across networks used in the IWF 125, but it can also be used in mobiles 110 which may also require clock rate matching to an independent source. In addition, the methods described can be used in a purely ISDN environment where separate, asynchronous ISDN clock sources are used.

Since the preferred embodiment of the inventive apparatus and method is a digital radiotelephone system, high BER rates are not unusual during transmission over the air interface. By using two bits to represent the clock compensation state and the remaining six bits as forward error correction, the susceptibility to the higher BER rates in the digital radiotelephone system is decreased. In the preferred embodiment two V.l lO frames are used for a total of eight E bits. To decrease the susceptibility of the high BER rates even further, more than two successive V.l lO frames may be employed resulting in more E bits used for forward error correction. In addition, other methods of forward error correction may be employed. For

example, by using one V.l lO frame having a total of four E bits, and using two E bits for clock compensation and the remaining E bits and extra S and X bits for forward error correction, the decreasing of susceptibility to high BER can still be accomplished. Likewise, anywhere from one of the E bits to four of the E bits used for clock compensation in a V.l lO frame could be used as a clock compensation state and forward error correction could be accomplished by repeating the particular state over a predetermined number of V.l lO frames. In this scenario, the initial V.l lO frame would have a determined state and successive V.l lO frames would contain the same state and, when the system is satisfied that the "correct" compensation state has been received, it will continue to receive different V.l lO frames containing a different clock compensation state. Any number of forward error correction schemes may be employed.

By incorporating the inventive apparatus and method into a radiotelephone system, such as GSM, the problem of matching asynchronous/independent clock sources is solved. The method alters data bits in a V.l lO frame by at least one full data bit thus ensuring that compression and optimization at the air interface does not lose the data bits that, if were fractional, would be lost. Reliability of the transmission is increased by forward error correcting the compensation states, thus reducing the method's susceptibility to errors due to high BER's. In addition, the use of simple data buffers, which are typically used in a data transfer environment, can be used to replace expensive and complicated phase difference detectors and the additional sampling techniques required for their use. What we claim is: