TECHNICAL FIELD

The present invention is related to clock extraction in systems that are effected by strong intersymbol interference. In particular, the invention presents a clock recovery device and method for a receiver. The clock recovery device and method can be used for an equalized system, e.g. a receiver with an adaptive equalizer. Thereby, the clock recovery device and method are able to perform timing recovery (TR) after the adaptive equalizer.

BACKGROUND

Next-generation ultra-high- speed short reach optical fiber links will utilize small, cheap, and low power consumption transceivers. All these requirements are mainly imposed due to the limited space of data center equipment. The transceivers should support intra- and inter-data center connections from a few hundred meters up to several tens of kilometers, respectively.

The preferred solution is to transmit 100+ Gbit/s per wavelength, which is very challenging when a very cheap solution is required. The coherent approach is out of scope, as it requires high power and expensive devices. Therefore, intensity modulation (IM) and direct detection (DD) schemes are preferred. The mature on-off keying modulation format, widely used in non-coherent systems has been also investigated for applications at 100+ Gbit/s per wavelength speed. However, such a solution would require expensive high-bandwidth optics and electronics. To overcome this drawback, advanced modulation formats supported by digital signal processing (DSP) have been investigated as an alternative technology to support 100-G, the most promising candidates being duobinary pulse amplitude modulation (DB-PAM-n), discrete multi-tone modulation (DMT), and carrier-less amplitude and phase modulation (CAP). All the aforementioned methods provide similar performance in IM-DD systems. However, the DB-PAM formats are more attractive, because they require a simple DSP. Optical transceivers used for data centers use very cheap components such as directly modulated lasers (DML) and electro absorption modulators (EML). DSP consumption and latency are very critical and only basic DSP functions are implemented in real products. The power of optical signal is almost proportional to the electrical signal that modulates the laser.

FIG. 10 shows in this respect a conventional IM-DD PAM transmission system. Forward- error correction (FEC) is necessary at higher data rates. These codes are often standardized but also they can be proprietary. After mapping bits output from the FEC into a PAM signal, the PAM signal can be pre-equalized to improve performance. A digital-to-analog converter (DAC) outputs an analog electrical signal that is often amplified by a modulator driver (MD). EMF/ DMF output optical signal may suffer from chromatic dispersion (CD) in longer links. Therefore, in some systems dispersion compensation fibers (DCF) or dispersion compensation modules (DCM) are used to compensate for CD. At the receiver side, a photo detector/diode (PDet) detects the optical signal. The PDet output is proportional to the optical signal power. The PDet output is amplified by using a transimpedance amplifier (TIA). PDet and TIA can be integrated in receive optical subassemblies (ROSA) that may include an automatic gain control circuit (AGC) to adjust electrical signal to an analog-to-digital (ADC) input when electronic equalization is used. The receiver can use feed-forward equalizer (FFE), decision feed-back equalizer (DFE), maximum likelihood sequence estimator (MFSE), or combine some of them at the receiver. FFE suffers from noise enhancement, DFE from error multiplication, while MFSE represents the best and most complex solution. At the end, hard FECs are normally used after the PAM demapper.

FIG. 11 shows a simplified Rx block diagram including TR blocks. The AGC block monitors signal power variations and produces almost constant signal swing that fits into the ADC input range. In this way the ADC is effectively used. The equalizer recovers signal suffering from noise and intersymbol interference (IS I). However, before the equalizer is activated, the local oscillator must be locked to the input signal, i.e. to the transmitter oscillator responsible for data clocking. These two oscillators must be synchronized. Small phase deviations are allowed, since it is impossible to perfectly track the transmitter clock source. Clock extraction is enabled by a phase detector (PD) that outputs information on whether the sampling clock is faster or slower. Since this information is noisy suffering from pattern-dependent noise, noise caused by amplifiers, component imperfections, etc., timing information must be filtered before entering/controlling the receiver oscillator, often realized as a voltage-controlled oscillator (VCO).

Timing information can be derived from the ADC output signal. The TR block includes PD, low-pass filter and VCO. VCO clock phase can be adjusted using sampling phase adjustment (SPA) circuit. Sampling phase optimization can be also supported by the FEC decoder that provides a number of FEC input errors (number of corrected errors). The best sampling phase should minimize this number.

IM-DD transmission systems can be modeled as shown in FIG. 12. The transmitted signal x is modified by the system transfer function H, which can be approximated by a linear system. In general, the system is nonlinear. The output signal is a convolution of the signal x and the system pulse response h:

The ISI spreads the input signal over 2n+l symbol intervals. Usually, the transfer function behaves as a low-pass filter, and high frequency components can be severely attenuated. An additive noise n additionally disturbs the signal x. The TR block gets a signal suffering from ISI and noise. TR designers count with noise, and practical TR solutions are less sensitive to noise in the specified working conditions. For example, a pre-FEC BER is directly related to the amount of noise that can be tolerated by the system. However, in systems using enhanced equalization techniques to cope with ISI caused by strong bandwidth limitations of optical and electrical components, the received signal contains insufficient clock information. In such systems, all known practical TR schemes fail, because the frequency content around Nyquist frequency is very pure.

In digital communication systems, the heart of each receiver is a clock recovery circuit that extracts frequency and phase from incoming data and forces a local clock source to control the sampling rate and the sampling phase of the ADC. Several phase detectors (PD) have been proposed for digital systems. It is common for all PDs that a timing error detector characteristics (PD output over symbol interval) is very similar to the sinusoidal function. One exception is a so-called„bang- bang“ PD, which has a timing error detector characteristic (TEDC) having sinusoidal shape in the presence of noise.

Another conventional PD works with one sample per symbol. Others PDs are used with two-fold oversampling. A conventional, so-called Gardner PD TEDC can, for example, be described for complex signals as: where T is symbol interval, x is input signal, t is sampling instant (between 0 and T), E is expectation, and * denotes conjugate complex operation. The squared Gardner PD (SGPD) performs well in FTN systems and can be described by:

In many implementations, the timing extraction is done before the equalizer (see FIG. 13). This works when ISI is not so serious. Anyway, TR jitter is smaller when ISI is not included (only noise is included). Thus, it is always better to have the signal only with noise. The medium ISI distorts the timing information and it can be tolerated in some systems. However, in systems with severe ISI this approach cannot work, because ISI timing degradation is too high so that:

1. The clock tone is very weak and the TR works with high probability of cycle slips.

2. The clock tone disappears and clock extraction is impossible.

3. The TEDC has no zero crossings. Clock extraction is impossible because there is no the equilibrium point.

4. The TEDC has multiple equilibrium points and hang-up regions. This causes cycle slips and long acquisition.

5. The TEDC has the DC component (asymmetrical TEDC). This increases the probability of cycle slips and makes the TR unstable. The main conclusion is therefore that the TR should be done after the equalizer in severe ISI scenarios. This can be relaxed by using the TR equalizer that is much simpler than the main equalizer.

In other words, to improve the clock performance, the signal before the TR should be equalized. When a static equalizer were implemented before the TR block - as shown in FIG. 14 (a) - the TR would perform best in static channels. However, the channel changes its characteristics over time, and the equalizer needs to track channel changes. Therefore, an adaptive equalizer would be desired - as illustrated in FIG. 14 (b). The adaptive equalizer can be a nonlinear feed-forward equalizer such as a Volterra filter. The adaptive equalizer varies taps to track channel changes. This will also cause the TR sampling phase change.

However, even in a static channel, the approaches shown in FIG. 14 (a) and (b) - i.e. simply providing TR after the equalizer - does not work, because the equalizer and TR try to compensate for phase shifts caused by both blocks. The sampling phase varies as shown in Fig. 14 (c). This will cause the equalizer taps walking in one direction. After some time, the central tap will not be in the center of pulse response. This will cause weaker equalizer performance. Also, it will cause TR instability. The worst scenario happens when the clock is practically lost and the sampling phase freely walks over many unit intervals in a short period of time. In this case, the equalizer still tracks sampling phase variations but the equalizer taps are incorrect, and the eye diagram is distorted with a BER of close to 0.5.

Thus, straightforward implementation of TR after equalization is not possible.

SUMMARY

In view of the above-mentioned problems and disadvantages, embodiments of the present invention aim to improve the current implementations. An objective is to provide a device and method that enable implementing TR after equalization. Thereby, the performance of the device and method should be high, and TR should be stable. The device and method should be applicable in scenarios with high ISI.

The objective is achieved by the embodiments of the invention as described in the enclosed independent claims. Advantageous implementations of the present invention are further defined in the dependent claims. Embodiments of the invention base generally on clock derivation after an adaptive equalizer in e.g. PAM-n transmission systems, which are seriously degraded by ISI caused by bandwidth limitations of system electrical and optical components. The embodiments of the invention base further on a recalculating of taps to enable the TR after equalization, and thereby have the following benefits:

1. The clock is derived after equalization, i.e. after an adaptive equalizer that decreases jitter caused by ISI.

2. The clock variations are much smaller than variations caused by the clock extracted before the equalizer.

3. Low-jitter clock improves the equalizer performance because the equalizer does not need to track large sampling phase variations caused by self -jitter.

4. The equalizer can easier track channel variations caused by system instabilities and channel imperfections.

5. The equalizer is not affected by fast deterministic jitter that can be tracked by the TR loop that is much faster than the equalizer updating speed.

6. The embodiments of the invention are applicable in both non-coherent and coherent systems, e.g. receivers.

A first aspect of the invention provides a clock recovery device for a receiver, the device comprising: an adaptive equalizer configured to equalize a digital receive signal, a timing recovery circuit configured to recover clock information from the equalized digital receive signal, and a calculation circuit configured to: calculate a first phase characteristic of a first set of equalizer coefficients currently set in the adaptive equalizer, calculate an initial phase characteristic of an initial set of equalizer coefficients set previously at initialization in the adaptive equalizer, calculate a first phase shift parameter indicating a phase shift between the first and the initial phase characteristic, calculate a first set of corrected equalizer coefficients based on the first set of equalizer coefficients and the first phase shift parameter, and update the first set of equalizer coefficients with the first set of corrected equalizer coefficients in the adaptive equalizer. Due to the calculation circuit of the clock recovery device of the first aspect, and the particular calculation it performs, i.e. to update the equalizer coefficients in the adaptive equalizer, a very stable TR after equalization is enabled. The clock recovery device is thus suited for being applied to systems with high ISI, without sacrificing TR performance. Channel changes may be tracked easier, and TR can be performed very fast. For instance, the device may be advantageously used in a coherent receiver.

In an implementation form of the first aspect, the calculation circuit is further configured to: calculate a second set of equalizer coefficients from the first set of corrected equalizer coefficients based on channel changes tracked by the adaptive equalizer and an adaptive algorithm.

In an implementation form of the first aspect, the adaptive algorithm is a mean square algorithm.

In an implementation form of the first aspect, the calculation circuit is further configured to: calculate a second phase characteristic of the second set of equalizer coefficients, calculate a second phase shift parameter indicating a phase shift between the second phase characteristic and the first phase characteristic or the initial phase characteristic, calculate a second set of corrected equalizer coefficients based on the second set of equalizer coefficients and the second phase shift parameter, and update the first set of corrected equalizer coefficients with the second set of corrected equalizer coefficients in the adaptive equalizer.

In an implementation form of the first aspect, equalizer coefficients are coefficients for taps of the adaptive equalizer, and a set of equalizer coefficients includes an equalizer coefficient per each tap of the adaptive equalizer.

In an implementation form of the first aspect, the calculation circuit is configured to: calculate a set of corrected equalizer coefficients based further on a calibration parameter, in particular a time- varying calibration parameter.

The calibration parameter improves BER and stability of the device.

In an implementation form of the first aspect, the calculation circuit is configured to: calculate the calibration parameter based on the first phase shift parameter or the second phase shift parameter. In an implementation form of the first aspect, the calculation circuit is configured to: calculate a phase shift characteristic of a set of equalizer coefficients based on a Fast Fourier Transform of the equalizer coefficients in the set of equalizer coefficients.

In an implementation form of the first aspect, the calculation circuit is further configured to: perform an inverse FFT on a set of corrected equalizer coefficients before updating the equalizer coefficients in the adaptive equalizer.

A second aspect of the invention provides a receiver, in particular a coherent receiver, including a clock recovery device according to the first aspect or any one of its implementation forms.

In an implementation form of the second aspect, the receiver further includes: an analog- to-digital converter, ADC, configured to convert an analog receive signal into the digital receive signal, wherein the clock recovery device is configured to provide the recovered clock information to the ADC.

The receiver of the second aspect enjoys the advantages and effects provided by the clock recovery device of the first aspect.

A third aspect of the invention provides a clock recovery method for a receiver, the method comprising: adaptively equalizing a digital receive signal, recovering clock information from the equalized digital receive signal, calculating a first phase characteristic of a first set of equalizer coefficients currently set, calculating an initial phase characteristic of an initial set of equalizer coefficients previously set at initialization, calculating a first phase shift parameter indicating a phase shift between the first and the initial phase characteristic, calculating a first set of corrected equalizer coefficients based on the first set of equalizer coefficients and the first phase shift parameter, and updating the first set of equalizer coefficients with the first set of corrected equalizer coefficients.

In an implementation form of the third aspect, the method further comprises: calculating a second set of equalizer coefficients from the first set of corrected equalizer coefficients based on tracked channel changes and an adaptive algorithm, calculating a second phase characteristic of the second set of equalizer coefficients, calculating a second phase shift parameter indicating a phase shift between the second phase characteristic and the first phase characteristic or the initial phase characteristic, calculating a second set of corrected equalizer coefficients based on the second set of equalizer coefficients and the second phase shift parameter, and updating the first set of corrected equalizer coefficients with the second set of corrected equalizer coefficients.

In an implementation form of the third aspect, the adaptive algorithm is a mean square algorithm.

In an implementation form of the third aspect, equalizer coefficients are coefficients for taps of an adaptive equalizer for adaptively equalizing the digital receive signal, and a set of equalizer coefficients includes an equalizer coefficient per each tap of the adaptive equalizer.

In an implementation form of the third aspect, the method further comprises: calculating a set of corrected equalizer coefficients based further on a calibration parameter, in particular a time- varying calibration parameter.

In an implementation form of the third aspect, the method further comprises: calculating the calibration parameter based on the first phase shift parameter or the second phase shift parameter.

In an implementation form of the third aspect, the method further comprises: calculating a phase shift characteristic of a set of equalizer coefficients based on a Fast Fourier Transform of the equalizer coefficients in the set of equalizer coefficients.

In an implementation form of the third aspect, the method further comprises: performing an inverse FFT on a set of corrected equalizer coefficients before updating the equalizer coefficients.

The method of the third aspect and its implementation forms achieve the same advantages and effects as described for the clock recovery device of the first aspect.

It has to be noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

FIG. 1 shows a clock recovery device according to an embodiment of the invention. FIG. 2 shows a receiver according to an embodiment of the invention.

FIG. 3 shows starting equalizer taps.

FIG. 4 shows equalizer taps.

FIG. 5 shows an equalizer phase characteristic.

FIG. 6 shows a phase shift parameter ps in symbol interval T.

FIG. 7 shows an equalizer taps walk.

FIG. 8 shows in (a) a phase shift parameter ps and a TR phase of a conventional clock recovery device, and shows in (b) a phase shift parameter ps and a TR phase of a clock recovery device according to an embodiment of the invention.

FIG. 9 shows a method according to an embodiment of the invention.

FIG. 10 shows an IM-DD PAM transmission system.

FIG. 11 shows basic Rx blocks including TR blocks.

FIG. 12 shows TR in systems with ISI and noise.

FIG. 13 shows TR before an equalizer. FIG. 14 shows in (a) TR after a static equalizer, shows in (b) TR after an adaptive equalizer, and shows in (c) TR sampling phase variations after an adaptive equalizer.

DETAILED DESCRIPTION OF EMBODIMENTS FIG. 1 shows a clock recovery device 100 according to an embodiment of the invention, which is suitable for a receiver, e.g. coherent receiver. The clock recovery device 100 comprises an adaptive equalizer 101, which is configured to equalize a digital receive signal x, comprises a timing recovery (TR) circuit 102, which is configured to recover clock information from the equalized digital receive signal y, and comprises a calculation circuit 103.

The calculation circuit 103 is in particular configured to calculate a first phase characteristic 105 - denoted a(k) - of a first set of equalizer coefficients w(k) 104 currently set in the adaptive equalizer 101. Further, it is configured to calculate an initial phase characteristic 107 - denoted a(0) - of an initial set of equalizer coefficients set previously at initialization in the adaptive equalizer 101. Then, it is configured to calculate a first phase shift parameter 106 - denoted ps - indicating a phase shift between the first and the initial phase characteristic a(0) and a(k), and to calculate a first set of corrected equalizer coefficients 108 - denoted w’(k) - based on the first set of equalizer coefficients w(k) and the first phase shift parameter ps. Then, it is configured to update the first set of equalizer coefficients w(k) with the first set of corrected equalizer coefficients w’(k) in the adaptive equalizer 101.

Thereby, equalizer coefficients are generally coefficients for taps of the adaptive equalizer 101, and a set of equalizer coefficients includes an equalizer coefficient per each tap of the adaptive equalizer 101. The adaptive equalizer 101 of the device 100 of FIG. 1 may start with w(0) equalizer coefficients with the a(0) initial phase characteristic. New equalizer coefficients w(k) for the equalizer taps may then be derived, e.g. after several updates. The first phase characteristic a(k) of the new coefficients is obtained. The ps is then calculated based on a(0) and a(k). The ps value is used to calculate the corrected (i.e. re-centered) equalizer coefficients w’(k). The coefficients w’(k) then replace the old coefficients used in the adaptive equalizer 101. This method performed by the device 100 is applicable in e.g. receivers 200, particularly coherent receivers. In the latter case, the signals x and y may be complex. The equalizer taps coefficients can be either real or complex.

FIG. 2 shows schematically parts of a receiver 200 according to an embodiment of the invention, which receiver 200 includes the clock recovery device 100 of FIG. 1. The receiver 200 further includes an ADC 201 , which is configured to convert an analog receive signal into the digital receive signal x (fed into the clock recovery device 100), wherein the clock recovery device 100 is further configured to provide the recovered clock information, i.e. the output of the TR circuit 102, to the ADC 201.

In the following, the method performed in the clock recovery device 100 or receiver 200, respectively, particularly in the calculation unit 103, is explained in more detail. Only real signals are considered in the following, but the same analyses and methods can be easily applied to complex signals.

The equalizer 101 uses a starting channel model (see FIG. 3) and tracks channel changes. The taps - i.e. equalizer coefficients of the taps - of the equalizer 101 can be updated using different adaptive algorithms. In the following, a linear equalizer 101 with n taps denoted by their coefficients w is considered. The real signal x before the equalizer 101 is equalized and the equalizer output is defined by:

The taps of the equalizer 101 can be updated, e.g. by a decision-directed least mean square algorithm defined by w(k + 1) = w(k) + mCe for the real input signal, where a vector w represents the equalizer coefficients for the taps, a vector x includes signal before the equalizer, and e is the equalizer error that is the difference between the output signal and the closest signal level. The parameter m defines an updating speed. Larger m values enables tracking fast channel changes, while smaller m values provide better performance. Very large m values may cause equalizer instability. Large m values are preferable in time-varying channels and it can bring very fast the system shown in Fig. 1 or FIG. 2 into the instable region. The channel response represented by taps coefficients Wi, i=0,l,..., n-1, provide information about the equalizer phase and amplitude in the frequency domain. The starting channel model i.e. the initial equalizer coefficients, are denoted by w(0). The Fourier transformation of the channel response represented by w(0) is W(0). That means W(0)=fft(w(0)). The coefficients in the frequency domain are W(i), i=0,l,..., n-1. The coefficients can be represented by amplitude and phase (polar form) so it can be written as W(i)=IW(j)lexp(ja(i)). For the channel response (w(0)) shown in FIG. 4, a phase transfer function can be calculated represented by a(0). This is shown in FIG. 5.

In a parallel realization, more symbols may be processed at the same time. For example, a CMOS clock can cover M=64 symbols. This means that 64 equalizers may work in parallel.

Equalizer taps will be 64 times recalculated, but they can be used in the equalizer only after they are calculated. When new taps are available, they can be used in the equalizer 101. New equalizer taps coefficients are denoted by W(k). Now, there is a new phase characteristic a(k) and the old, initial one a(0). Each of them has n values. When n is even it holds a(j)=-a(n-j+l). The coefficients can be written as a(0,j). The phase shift done by new coefficients can be calculated by the phase shift parameter:

The phase shift is illustrated in FIG. 6. It changes over time and the central taps will move to the right side. When they approach the equalizer limits, the central taps are located in the end of filter. This case is shown in FIG. 7. In this situation, the equalizer produces a lot of errors and gets instable.

The phase shift parameter ps can be calculated based on filter taps in the time domain (wi, i=0,l,..., n-1): k2

j=kl The simplest realization uses f(0,j)=f(k,j)=j. However, these coefficients can be optimized to achieve the best performance. The optimization can be done only around the central tap. For example, only f of five the most important taps can be optimized. The optimum value provides the smallest sampling phase variations. The TR phase would conventionally try to follow sampling phase changes caused by the equalizer. This is shown in FIG. 8 (a). However, this ends as already mentioned. In order to hinder the sampling phase walk, the calculation circuit 103 recalculates the equalizer taps coefficients by, for instance:

W'(j) = W 0) ^ex P (— /4p/ (/) (ps - d)/h )

/ = 0,1,

The optional parameter d helps to improve BER and system stability. This parameter may be defined during calibration, and may be changed over time, in order to improve the device performance. Also, a(0) can be replaced after some time by using the current FFE taps. The new taps coefficients W’(j) can be used directly in the frequency domain equalizer. They can we transferred in time domain by w”=ifft(W’) and used in time-domain equalizer. The equalizer 101 and TR circuit 102 are stable in this case that is visualized in Fig. 8 (b). TR variations are only caused by self jitter and equalizer variations are caused by noise and updating factor m. The TR updating speed is much larger than the updating of the equalizer 101. In case of fast deterministic jitter, the TR circuit 101 will track jitter variations. The equalizer 101 will not be effected by any jitter because the taps are always re-centered. It means that the equalizer 101 will not be able to track any phase changes.

An algorithm performed by the device 100 or receiver 200 can be summarized in following steps:

1. Set the starting equalizer taps coefficients (starting channel model).

2. Calculate the starting channel model phase characteristic 107.

3. Acquire a clock. The TR is stable but noisy.

4. Calculate the new channel model (equalizer taps coefficients 104). 5. Calculate the new channel model phase characteristic 105.

6. Calculate phase shift parameter 106 caused by the new channel model. 7. Recalculate the new equalizer coefficients 104 by shifting new taps by the calculated phase shift to obtain the corrected equalizer coefficients 108.

8. After acquiring the channel, replace the starting channel model by the current channel model periodically. Change optionally the parameter d by the shift introduced by this replacement.

FIG. 9 shows a method 900 according to an embodiment of the invention. The method 900 may be performed by the device 100 of FIG. 1 or the receiver 200 of FIG. 2.

The method 900 includes a step 901 of adaptively equalizing a digital receive signal. This may be done by the adaptive equalizer 101. The method further includes a step 902 of recovering clock information from the equalized digital receive signal. This may be done by the TR circuit 102. The method also includes further steps, which may be done by the calculation circuit 103, namely: a step 903 of calculating a first phase characteristic 105 of a first set of equalizer coefficients 104 currently set (e.g. in the adaptive equalizer 101), a step 904 of calculating an initial phase characteristic 107 of an initial set of equalizer coefficients previously set at initialization (e.g. in the adaptive equalizer 101), a step 905 of calculating a first phase shift parameter 106 indicating a phase shift between the first and the initial phase characteristic 105 and 107, a step 906 of calculating a first set of corrected equalizer coefficients 108 based on the first set of equalizer coefficients 104 and the first phase shift parameter 106, and a step 907 of updating the first set of equalizer coefficients 104 with the first set of corrected equalizer coefficients 108.

The present invention has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed invention, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word“comprising” does not exclude other elements or steps and the indefinite article“a” or“an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.