Title:
CLOCK REPLAY CIRCUIT AND CLOCK REPLAY METHOD
Document Type and Number:
WIPO Patent Application WO/2012/029597
Kind Code:
A1
Abstract:
The present invention can be applied to high-speed communication of an equalization technique to a duobinary signal, that proactively uses inter-code interference. In such applications, a clock replay circuit that accurately detects clock timing is required due to the limited margin available for clock timing. Provided is a duobinary clock replay circuit provided with a phase detection circuit that detects phase displacement between an input signal and a clock signal and can output binary values in the current timing by using decision results and previously-assessed binary values, by comparing input signals that have been equalized to duobinary waveforms with a plurality of threshold values.
Inventors:
HASEGAWA HIDEYUKI (JP)
Application Number:
PCT/JP2011/068996
Publication Date:
March 08, 2012
Filing Date:
August 17, 2011
Export Citation:
Assignee:
NEC CORP (JP)
HASEGAWA HIDEYUKI (JP)
HASEGAWA HIDEYUKI (JP)
International Classes:
H04L7/02; H03K5/26; H03L7/08; H03L7/085; H04L25/497
Domestic Patent References:
| WO2010032699A1 | 2010-03-25 | |||
| WO2007037312A1 | 2007-04-05 |
Attorney, Agent or Firm:
IKEDA, Noriyasu et al. (JP)
Noriyasu Ikeda (JP)
Noriyasu Ikeda (JP)
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